Xilinx Constraints Guide

Chapter 2: Entry Strategies for Xilinx Constraints
ISE Design Suite
PlanAhead
To set implementation constraints in ISE® Design Suite:
• For FPGA devices, the implementation process properties specify how a design is
translated, mapped, placed, and routed. You can set multiple properties to control
the implementation processes.
• For CPLD devices, the implementation process properties specify how a design is
translated and fit.
For more information, see the ISE Design Suite help for the Process Properties dialog box.
You can use the PlanAhead software either before or after synthesis. The PlanAhead
software supports the following devices:
• Virtex®-4 devices and higher
• Spartan®-3 devices and higher
The PlanAhead software allows you to drag-and-drop placement constraints, including:
• Pinout
• Logic placement
• Area
For more information, see the PlanAhead User Guide (UG632).
Assigning Placement Constraints
For FPGA devices, you can use the PlanAhead software to enter placement constraints
that control:
• I/O pin and logic assignments
• Global logic placement
• Area group assignment
The PlanAhead software runs automatically at various stages of the design process
to allow you to analyze the design and to apply placement constraints. A simplified
version of the PlanAhead software is invoked from ISE® Design Suite to enable only
the types of features required to perform the selected tasks. The standalone PlanAhead
software has many more features available.
When the PlanAhead software is invoked from ISE Design Suite, it is a separate CPU
process and does not communicate realtime with ISE Design Suite as some other tools
do. In order to prevent data mismatch or out of sync issues, do not update ISE Design
Suite source files while the PlanAhead software is running .
When the PlanAhead software is invoked, the appropriate source files are passed to the
PlanAhead software to populate the PlanAhead Project. When the PlanAhead Project is
saved, only the modified UCF files are passed back to ISE Design Suite to update the
Project. These input source files vary depending on the process step invoked.
For more information on the types of files passed, see the Pin Assignment and
Floorplanning and Placement Constraints sections later in this chapter. The following
sections cover strategies for entering placement constraints using the PlanAhead
software.
Constraints Guide
40 www.xilinx.com UG625 (v. 13.2) July 6, 2011