Xilinx Constraints Guide

Multi-Cycle Paths
Chapter 3: Timing Constraint Strategies
The generic syntax for defining a timing ignore (TIG) between time groups is:
TIMESPEC "TSid" = FROM "SRC_GRP" TO "DST_GRP" TIG;
In the FROM-TO TIG example, the SRC_GRP defines the set of source registers in
which path tracing will begin from while the DST_GRP defines the set of destination
registers the path tracing will end at. All paths that begin in the SRC_GRP and end in
the DST_GRP will be ignored.
The specific syntax for this example is:
NET “CLK1” TNM_NET = FFS “GRP_1”;
NET “CLK2” TNM_NET = FFS “GRP_2”;
TIMESPEC TS_Example = FROM “GRP_1” TO “GRP_2” TIG;
A multi-cycle path is a path in which data is transferred from source to destination
register at a rate that is less than the clock frequency defined in the PERIOD specification.
This scenario most often occurs when the registers are gated with a common clock
enable signal. By defining a multi-cycle path, the timing constraints for these registers
will be relaxed over the default PERIOD constraint, and the implementation tools will
be able to prioritize the implementation of these paths appropriately.
To specify the FROM-TO multi-cycle constraint:
1. Define a PERIOD constraint for the common clock domain
2. Define a set of registers based on a common clock enable signal
3. Define a FROM-TO multi-cycle constraint describing the new timing requirement
Example
This example shows a hypothetical case in which a path between two registers is clocked
by a common clock enable signal. The clock enable is toggled at a rate that is one half of
the reference clock. A block diagram of the example circuit is shown in the figure below.
The generic syntax for defining a multi-cycle path between time groups is:
TIMESPEC “TSid” = FROM “MC_GRP” TO “MC_GRP” value;
In the FROM-TO multi-cycle example, the MC_GRP defines the set of registers which
are driven by a common clock enable signal. All paths that begin in the MC_GRP and
end in the MC_GRP will have the multi-cycle timing requirement applied to them while
paths into and out of the MC_GRP will be analyzed with the appropriate PERIOD
specification.
Constraints Guide
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