Xilinx Constraints Guide

Architecture Support
Applicable Elements
Propagation Rules
KEEP_HIERARCHY EXAMPLE
Applies to all FPGA devices and all CPLD devices.
Attached to logical blocks, including blocks of hierarchy or symbols.
Applies to the entity, module, or signal to which it is attached.
Syntax
Chapter 4: Xilinx Constraints
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to the entity or module symbol
• Attribute Name
KEEP_HIERARCHY
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute keep_hierarchy : string;
Specify the VHDL constraint as follows:
attribute keep_hierarchy of architecture_name: architecture is {TRUE|FALSE|SOFT};
The default is false for FPGA devices and true for CPLD devices.
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
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