Xilinx Constraints Guide

MIODELAY_GROUP (MIODELAY Group)
Architecture Support
Applicable Elements
Propagation Rules
The MIODELAY_GROUP (MIODELAY Group) constraint:
• Is a design implementation constraint.
Chapter 4: Xilinx Constraints
• Combines two or more IODELAY_GROUP constraints into a single Master
IODELAY_GROUP to enable automatic replication and placement of IDELAYCTRL
constraints in a design.
MIODELAY_GROUP applies to Virtex®-4 and Virtex-5 devices. For Virtex-4 devices,
MIODELAY_GROUP is supported only when using the Timing Driven Pack and
Placement Option in MAP.
MIODELAY_GROUP is applied to two or more defined IODELAY_GROUPs.
MIODELAY_GROUP is applied to an existing IODELAY_GROUP. The
MIODELAY_GROUP is propagated to all of the design elements that belonged to the
original IODELAY_GROUP. It is illegal to attach MIODELAY_GROUP to a net, signal,
or pin.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF Syntax
MIODELAY_GROUP "master_group_name" = iodelay_group1 iodelay_group2 ... ;
where
• master_group_name
– represents the master group being defined
– contains all of the elements in iodelay_group1 and iodelay_group2
• iodelay_group1 and iodelay_group2 are predefined IODELAY groups
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 189