Xilinx Constraints Guide
Xilinx Constraints Guide
Xilinx Constraints Guide
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IOSTANDARD (Input Output Standard)<br />
The IOSTANDARD (Input Output Standard) constraint:<br />
• Is a basic mapping constraint.<br />
• Is a synthesis constraint.<br />
IOSTANDARD for FPGA Devices<br />
Use IOSTANDARD to assign an I/O standard to an I/O primitive.<br />
Chapter 4: <strong>Xilinx</strong> <strong>Constraints</strong><br />
All components with IOSTANDARD must follow the same placement rules (banking<br />
rules) as the SelectIO components. See the <strong>Xilinx</strong>® Libraries <strong>Guide</strong>s for information on<br />
the banking rules for each architecture. For descriptions of the supported I/O standards,<br />
see the device data sheet.<br />
For Spartan®-3, Spartan-3A, Spartan-3E, Virtex®-4, and Virtex-5 devices, the<br />
recommended procedure is to attach IOSTANDARD to a buffer component instead<br />
of using the SelectIO variants of a component. For example, use an IBUF with the<br />
IOSTANDARD=HSTL_III constraint instead of the IBUF_HSTL_III component.<br />
For Spartan-3, Spartan-3A, Spartan-3E, Virtex-4, and Virtex-5 devices, differential<br />
signaling standards apply to IBUFDS, IBUFGDS, OBUFDS, and OBUFTDS only (not<br />
IBUF or OBUF).<br />
IOSTANDARD for CPLD Devices<br />
Architecture Support<br />
Applicable Elements<br />
Propagation Rules<br />
You can apply IOSTANDARD to I/O pads of CoolRunner-II devices to specify both<br />
input threshold and output VCCIO voltage. For supported values, see the device data<br />
sheet.<br />
The CPLD fitter automatically groups outputs with compatible IOSTANDARD settings<br />
into the same bank when no location constraints are specified.<br />
Applies to all FPGA devices and CoolRunner-II CPLD devices.<br />
To see which design elements can be used with which device families, see the Libraries<br />
<strong>Guide</strong>s. For more information, see the device data sheet.<br />
• IBUF, IBUFG, OBUF, OBUFT<br />
• IBUFDS, IBUFGDS, OBUFDS, OBUFTDS<br />
• Output Voltage Banks<br />
It is illegal to attach IOSTANDARD to a net or signal except when the signal or net is<br />
connected to a pad. In this case, IOSTANDARD is treated as attached to an IOB instance<br />
(IBUF, OBUF, IOB FF). When attached to a design element, IOSTANDARD propagates<br />
to all applicable elements in the hierarchy within the design element.<br />
Syntax Examples<br />
The following examples show how to use this constraint with particular tools or<br />
methods. If a tool or method is not listed, you cannot use this constraint with it.<br />
<strong>Constraints</strong> <strong>Guide</strong><br />
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 147