Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
KEEP (Keep)
The KEEP (Keep) constraint:
• Is an advanced mapping constraint.
• Is a synthesis constraint.
Architecture Support
Applicable Elements
When a design is mapped, some nets may be absorbed into logic blocks. When a net
is absorbed into a block, it can no longer be seen in the physical design database. This
may happen, for example, if the components connected to each side of a net are mapped
into the same logic block. The net may then be absorbed into the block containing the
components. KEEP prevents this from happening.
KEEP is translated into an internal constraint known as NOMERGE when targeting an
FPGA. Messaging from the implementation tools therefore refers to the system property
NOMERGE, not KEEP. In addition to TRUE and FALSE, synthesis (XST) accepts and
additional SOFT value that instructs the tool to preserve the designated net, but also
prevents it from attaching a NOMERGE constraint to this net in the synthesized netlist.
As a result, the net is preserved during synthesis, but implementation tools are given all
freedom to handle it. Conceptually, you are specifying a KEEP=TRUE for synthesis only,
but a KEEP=FALSE for implementation tools.
Applies to all FPGA devices and all CPLD devices.
Applies to signals.
Propagation Rules
Applies to the signal to which it is attached.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a net
• Attribute Name
KEEP
• Attribute Values
TRUE
FALSE
SOFT (XST only)
VHDL Syntax
Declare the VHDL constraint as follows:
attribute keep : string;
Specify the VHDL constraint as follows:
attribute keep of signal_name: signal is “{TRUE|FALSE|SOFT}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
150 www.xilinx.com UG625 (v. 13.2) July 6, 2011