Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
NODELAY (No Delay)
The NODELAY (No Delay) constraint:
• Is an advanced mapping constraint.
The default configuration of IOB flip-flops in designs includes an input delay that
results in an external hold time on the input data path. This delay can be removed
by placing NODELAY on input flip-flops or latches, resulting in a smaller setup
time but a positive hold time. The input delay element is active in the default
configuration for Spartan®-3, Spartan-3A, and Spartan-3E devices.
• Can be attached to I/O symbols and the following special function access symbols:
– TDI
– TMS
– TCK
Architecture Support
Applicable Elements
Spartan-3, Spartan-3A, and Spartan-3E devices are supported.
IOBDELAY=NONE, which is applicable to all FPGA devices, is the preferred method
of applying this constraint. For more information see IOBDELAY (Input Output Block
Delay).
Input register
Propagation Rules
You can also attach NODELAY to a net connected to a pad component in a User
Constraints File (UCF). NGDBuild transfers the constraint from the net to the pad
instance in the NGD file so that it can be processed by the mapper. Use the following
UCF syntax:
NET “ net_name” NODELAY;
NODELAY is illegal when attached to a net or signal except when the net or signal is
connected to a pad. In this case, NODELAY is treated as attached to the pad instance.
When attached to a design element, NODELAY is propagated to all applicable elements
in the hierarchy within the design element.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a valid instance
• Attribute Name
NODELAY
• Attribute Values
TRUE
FALSE
Constraints Guide
190 www.xilinx.com UG625 (v. 13.2) July 6, 2011