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Xilinx Constraints Guide

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Chapter 2: Entry Strategies for <strong>Xilinx</strong> <strong>Constraints</strong><br />

Physical <strong>Constraints</strong> File (PCF)<br />

The Native Generic Database (NGD) file produced when a design netlist is read into<br />

the <strong>Xilinx</strong>® ISE® Design Suite may contain a number of logical constraints. These<br />

constraints originate in any of these sources.<br />

• An attribute assigned within a schematic or Hardware Description Language (HDL)<br />

file<br />

• A constraint entered in a User <strong>Constraints</strong> File (UCF)<br />

• A constraint appearing in an Netlist <strong>Constraints</strong> File (NCF) produced by a CAE<br />

vendor toolset<br />

Logical constraints in the NGD file are read by MAP. MAP uses some of the constraints<br />

to map the design and converts logical constraints to physical constraints. MAP then<br />

writes these physical constraints into a Physical <strong>Constraints</strong> File (PCF).<br />

The PCF file is an ASCII file containing two separate sections:<br />

• A section for those physical constraints created by the mapper<br />

• A section for physical constraints entered by the user<br />

The mapper section is rewritten every time you run the mapper.<br />

Mapper-generated physical constraints appear first in the file, followed by user physical<br />

constraints. In the event of conflicts between mapper-generated and user constraints,<br />

user constraints are read last, and override mapper-generated constraints.<br />

The beginning of the mapper-generated section is indicated by SCHEMATIC START.<br />

The end of this section is indicated by SCHEMATIC END. Enter user-generated<br />

constraints, such as timing constraints, after SCHEMATIC END.<br />

You can write user constraints directly into the file, or you can write them indirectly (or<br />

undo them) from within the FPGA Editor. For more information on constraints in the<br />

FPGA Editor, see the FPGA Editor help.<br />

Note Whenever possible, you should add design constraints to the HDL, schematic, or<br />

UCF, instead of PCF. This simplifies design archiving and improves design role checking.<br />

The PCF file is an optional input to PAR, FPGA Editor, TRACE, NetGen, and BitGen.<br />

The file may contain any number of constraints, and any number of comments, in any<br />

order. A comment consists of either a pound sign (#) or double slashes (//) followed by<br />

any number of other characters up to a new line. Each comment line must begin with a<br />

pound sign (#) or double slashes (//).<br />

The structure of the PCF file is as follows.<br />

schematic start;<br />

translated schematic and UCF and NCF constraints in PCF format<br />

schematic end;<br />

user-entered physical constraints<br />

Caution! Put all user-entered physical constraints after the schematic end statement.<br />

Any constraints preceding this section or within this section may be overwritten or ignored.<br />

Do not edit the schematic constraints. They are overwritten every time the mapper<br />

generates a new PCF file.<br />

Global constraints need not be attached to any object, but should be entered in a<br />

constraints file.<br />

Indicate the end of each constraint statement with a semicolon.<br />

<strong>Constraints</strong> <strong>Guide</strong><br />

36 www.xilinx.com UG625 (v. 13.2) July 6, 2011

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