Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
TIG (Timing Ignore)
The TIG (Timing Ignore) constraint:
• Is a timing constraint and a synthesis constraint.
• Causes paths that fan forward from the point of application (of TIG) to be treated as
if they do not exist (for the purposes of timing analysis) during implementation.
• Can be applied relative to a specific timing specification.
• Can have any of the following values:
– Empty (global TIG that blocks all paths)
– A single TSid to block
– A comma separated list of TSids to block, for example
• Is fully supported by XST.
Example
Architecture Support
Applicable Elements
NET “RESET” TIG=TS_fast, TS_even_faster;
Applies to FPGA devices. Does not apply to CPLD devices.
• Nets
• Pins
• Instances
Propagation Rules
If TIG is attached to a net, primitive pin, or macro pin, all paths that fan forward from the
point of application of the constraint are treated as if they do not exist for the purposes
of timing analysis during implementation. In the following figure:
• NET C is ignored
• The lower path of NET B that runs through the two OR gates is not ignored
TIG Example
Constraints Guide
276 www.xilinx.com UG625 (v. 13.2) July 6, 2011