Xilinx Constraints Guide

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Chapter 4: Xilinx Constraints PlanAhead Syntax For more information about using the PlanAhead software to create constraints, see Floorplanning the Design in the PlanAhead User Guide (UG632). See PlanAhead in this Guide for information about: • Defining placement constraints • Assigning placement constraints • Defining I/O pin configurations • Floorplanning and placement constraints FPGA Editor Syntax To set constraints, in the FPGA Editor main window, click Properties of Selected Items from the Edit menu. To set PERIOD constraint, click Properties of Selected Items from the Edit menu with a net selected. You can set the constraint from the Physical Constraints tab. PERIOD Specifications on CLKDLLs, DCMs, PLLs, and MMCMs When a Timing Name (TNM) or Timing Name Net (TNM_NET) property traces into an input pin on a DLL, DCM, PLL, or MMCM, it is handled as described in the following paragraphs. The checking and transformations described are performed by the logical TimeSpec processing code, which is run during NGDBuild, or the translate process. (The checking timing specifications status message indicates that the logical TimeSpec processing is being run.) The modifications are saved in the built NGD, used by the Mapper and the Map phase passed through the PCF file to the Place and Route (PAR) phase and TRACE. However, note that the data saved in the built NGD is distinct from the original TimeSpec user-applied properties, which are left unchanged by this process. Therefore, the Constraints Editor does not see these new groups or specifications, but sees (and possibly modifies) the original user-applied ones. Conditions for Transformation When a TNM_NET property is traced into the CLKIN pin of a DLL, DCM, PLL, or MMCM, the TNM group and its usage are examined. The TNM is pushed through the CLKDLL, DCM, PLL, or MMCM (as described below) only if the following conditions are met: • The TNM group is used in exactly one PERIOD specification. • The TNM group is not used in any FROM-TO or OFFSET specifications. • The TNM group is not referenced in any user group definition. If any of the above conditions are not met, the TNM is not be pushed through the CLKDLL/DCM/PLL/MMCM, and a warning message is issued. This does not prevent the TNM from tracing into other elements in the standard fashion, but if it traces nowhere else, and is used in a specification, an error results. Definition of New PERIOD Specifications If the CLK0 output on the CLKDLL, DCM, PLL, or MMCM is the only one being used (and neither CLKIN_DIVIDE_BY_2 nor CLKOUT_PHASE_SHIFT=FIXED are used), the original PERIOD specification is simply transferred to that clock output. Otherwise, for each clock output pin used on the CLKDLL, DCM, PLL, or MMCM, a new TNM group is created on the connected net, and a new PERIOD specification is created for that group. The following table shows how the new PERIOD specifications is defined, assuming an original PERIOD specification named TS_CLKIN. Constraints Guide 214 www.xilinx.com UG625 (v. 13.2) July 6, 2011
New PERIOD Specifications Output Pin Period Value Phase Shift Duty Cycle Chapter 4: Xilinx Constraints CLK0 TS_CLKIN * 1 none Copied from TS_CLKIN if DUTY_CYCLE_CORRECTION is FALSE. Otherwise, 50% CLK90 TS_CLKIN * 1 PHASE + (clk0_period * 1/4) Copied from TS_CLKIN if DUTY_CYCLE_CORRECTION is FALSE. Otherwise, 50% CLK180 TS_CLKIN * 1 PHASE + (clk0_period * 1/2) Copied from TS_CLKIN if DUTY_CYCLE_CORRECTION is FALSE. Otherwise, 50% CLK270 TS_CLKIN * 1 PHASE + (clk0_period * 3/4) Copied from TS_CLKIN if DUTY_CYCLE_CORRECTION is FALSE. Otherwise, 50% CLK2X TS_CLKIN / 2 none 50% CLK2X180 TS_CLKIN / 2 PHASE + (clk2X_period * 1/2) 50% CLKDV TS_CLKIN * clkdv_divide CLKFX where clkdv_divide is the value of the CLKDV_DIVIDE property (default 2.0) CLKFX180 TS_CLKIN / clkfx_factor where clkfx_factor is the value of the CLKFX_MULTIPLY property (default 4.0) divided by the value of the CLKFX_DIVIDE property (default 1.0). none 50% except for non-integer divides in high-frequency mode (CLKDLLHF, or DCM with DLL_FREQUENCY_MODE= HIGH): none PHASE + (clkfx_period * 1/2) 50% CLKDV_DIVIDE 1.5 33.33% HIGH 2.5 40.00% HIGH 3.5 42.86% HIGH 4.5 44.44% HIGH 5.5 45.45% HIGH 6.5 46.15% HIGH 7.5 46.67% HIGH The Period Value shown in this table assumes that the original specification, TS_CLKIN, is expressed as a time. If TS_CLKIN is expressed as a frequency, the multiply or divide operation is reversed. If the DCM attribute FIXED_PHASE_SHIFT or VARIABLE_PHASE_SHIFT is used, the amount of phase specified is also included in the PHASE value. Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 215
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Constraints Guide UG625 (v. 13.2) J
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Table of Contents Revision History
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IBUF_DELAY_VALUE (Input Buffer Dela
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Constraint Types Attributes and Con
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Grouping Constraints for Timing Cha
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The name qualifier can include the
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Physical Constraints Mapping Note T
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Placement Constraints Chapter 1: Co
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Routing Directives Routing directiv
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Timing Constraints Chapter 1: Const
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UCF Timing Constraint Support From-
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Timing Model Constraint Priority Ch
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Chapter 2 Entry Strategies for Xili
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Constraint Schematic VHDL Verilog L
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An attribute can be declared in an
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User Constraints File (UCF) UCF Flo
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Syntax Chapter 2: Entry Strategies
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Entering Multiple Constraints File
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Chapter 2: Entry Strategies for Xil
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Running Constraints Editor As a Sta
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Defining I/O Pin Configurations Cha
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Placement LOC Constraint Assignment
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Verilog Example -------------module
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Chapter 2: Entry Strategies for Xil
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Timing Specification Priorities Cha
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Timing Constraint Strategies Chapte
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Chapter 3: Timing Constraint Strate
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The global OFFSET IN constraint for
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The PERIOD constraint syntax for th
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Example Chapter 3: Timing Constrain
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Chapter 3: Timing Constraint Strate
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The global OFFSET OUT constraints f
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Multi-Cycle Paths Chapter 3: Timing
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Xilinx Constraints Each Xilinx® co
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RANGE Chapter 4: Xilinx Constraints
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Chapter 4: Xilinx Constraints Range
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COMPRESSION GROUP PLACE Chapter 4:
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Defining From Timing Groups Chapter
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BEL (BEL) The BEL (BEL) constraint:
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BLKNM (Block Name) Architecture Sup
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BUFG (BUFG) The BUFG (BUFG) constra
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Clock Dedicated Route (CLOCK_DEDICA
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COMPGRP (Component Group) Architect
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• S_SELECTMAP16 Slave SelectMAP M
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Verilog Syntax Chapter 4: Xilinx Co
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PCF Syntax CONFIG DCI_CASCADE = ",
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Default (DEFAULT) Chapter 4: Xilinx
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Example (* KEEPER = “TRUE” *) D
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DIFF_TERM (Diff_Term) Architecture
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DIRECTED_ROUTING (Directed Routing)
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DISABLE (Disable) The DISABLE (Disa
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DRIVE (Drive) The DRIVE (Drive) con
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XCF Syntax MODEL “entity_name”
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ENABLE (Enable) The ENABLE (Enable)
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ENABLE_SUSPEND (Enable Suspend) Arc
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Constraints Editor Syntax Chapter 4
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax NET “signal_na
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Chapter 4: Xilinx Constraints You a
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HBLKNM (Hierarchical Block Name) Ar
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HIODELAY_GROUP (HIODELAY Group) Arc
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HU_SET (HU Set) The HU_SET (HU Set)
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IBUF_DELAY_VALUE (Input Buffer Dela
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IFD_DELAY_VALUE (IFD Delay Value) T
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IN_TERM (In Term) Architecture Supp
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INREG (Input Registers) Architectur
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IOB (IOB) The IOB constraint: • I
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IOBDELAY (Input Output Block Delay)
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IODELAY_GROUP (IODELAY Group) Limit
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IOSTANDARD (Input Output Standard)
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Pinout and Area Constraints Editor
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Architecture Support Applicable Ele
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Keeper (KEEPER) Architecture Suppor
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LOC (Location) The LOC (Location) c
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Chapter 4: Xilinx Constraints The w
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LOC Range Constraint Examples Const
Page 163 and 164: PlanAhead Syntax Chapter 4: Xilinx
Page 165 and 166: Schematic LOC=P17 Chapter 4: Xilinx
Page 167 and 168: Example One Chapter 4: Xilinx Const
Page 169 and 170: Slices Prohibited Example Two Chapt
Page 171 and 172: LOCK_PINS (Lock Pins) Architecture
Page 173 and 174: where value is any chosen name unde
Page 175 and 176: MAP (Map) Architecture Support Appl
Page 177 and 178: Specify the Verilog constraint as f
Page 179 and 180: Architecture Support Applicable Ele
Page 181 and 182: MAXDELAY (Maximum Delay) Architectu
Page 183 and 184: PCF Syntax item MAXDELAY = maxvalue
Page 185 and 186: MAXSKEW (Maximum Skew) The MAXSKEW
Page 187 and 188: FPGA Editor Syntax Chapter 4: Xilin
Page 189 and 190: MIODELAY_GROUP (MIODELAY Group) Arc
Page 191 and 192: VHDL Syntax Declare the VHDL constr
Page 193 and 194: UCF and NCF Syntax Chapter 4: Xilin
Page 195 and 196: where Chapter 4: Xilinx Constraints
Page 197 and 198: Falling Edge Constraints Chapter 4:
Page 199 and 200: PlanAhead Syntax Chapter 4: Xilinx
Page 201 and 202: where Chapter 4: Xilinx Constraints
Page 203 and 204: UCF Syntax NET “clock” TNM_NET
Page 205 and 206: Verilog Syntax Chapter 4: Xilinx Co
Page 207 and 208: Attribute OUT_TERM: string; Specify
Page 209 and 210: TIMESPEC PERIOD Method Chapter 4: X
Page 211 and 212: Examples of a Primary Clock with De
Page 213: where • period is the required cl
Page 217 and 218: Post CRC (POST_CRC) Architecture Su
Page 219 and 220: Post CRC Frequency (POST_CRC_FREQ)
Page 221 and 222: Post CRC Signal (POST_CRC_SIGNAL) A
Page 223 and 224: PRIORITY (Priority) Architecture Su
Page 225 and 226: The following are not supported: Ch
Page 227 and 228: PULLDOWN (Pulldown) Architecture Su
Page 229 and 230: PULLUP (Pullup) Architecture Suppor
Page 231 and 232: PWR_MODE (Power Mode) Architecture
Page 233 and 234: REG (Registers) The REG (Registers)
Page 235 and 236: RLOC (Relative Location) The Relati
Page 237 and 238: RLOC = X3Y4 Chapter 4: Xilinx Const
Page 239 and 240: Linking Sets Set Linkage Chapter 4:
Page 241 and 242: Chapter 4: Xilinx Constraints by th
Page 243 and 244: Linking Two HU_SET Sets Chapter 4:
Page 245 and 246: Specify the VHDL constraint as foll
Page 247 and 248: Chapter 4: Xilinx Constraints Diffe
Page 249 and 250: H_SET (H Set) Chapter 4: Xilinx Con
Page 251 and 252: Chapter 4: Xilinx Constraints The n
Page 253 and 254: Syntax Examples Chapter 4: Xilinx C
Page 255 and 256: RLOC_RANGE (Relative Location Range
Page 257 and 258: where the relative X values (m1 and
Page 259 and 260: VHDL Syntax Declare the VHDL constr
Page 261 and 262: UCF and NCF Syntax NET “mysignal
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VHDL Syntax Chapter 4: Xilinx Const
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SLOW (Slow) The SLOW (Slow) constra
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STEPPING (Stepping) Architecture Su
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VHDL Syntax Chapter 4: Xilinx Const
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Chapter 4: Xilinx Constraints The f
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TIMEGRP (Timing Group) The TIMEGRP
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Defining Latch Subgroups by Gate Se
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Chapter 4: Xilinx Constraints When
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PCF Syntax TIMEGRP name; TIMEGRP na
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Separators FROM-TO Syntax TIMESPEC
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TNM (Timing Name) Chapter 4: Xilinx
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Chapter 4: Xilinx Constraints A qua
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
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Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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UCF and NCF Syntax Chapter 4: Xilin
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Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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UCF and NCF Syntax Chapter 4: Xilin
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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