Xilinx Constraints Guide

IOBDELAY (Input Output Block Delay)
The IOBDELAY (Input Output Block Delay) constraint:
• Is a basic mapping constraint.
Chapter 4: Xilinx Constraints
• Specifies how the input path delay elements in all devices are to be programmed.
There are two possible destinations for input signals:
• The local IOB input FF
• A load external to the IOB
Architecture Support
Applicable Elements
Propagation Rules
Xilinx® devices allow a delay element to delay the signal going to one or both of these
destinations.
IOBDELAY cannot be used concurrently with No Delay (NODELAY).
• NONE sets the delay OFF for both the IBUF and IFD paths.
– The following statement sets the delay OFF for the IBUF and IFD paths.
INST “xyzzy” IOBDELAY=NONE
– For Spartan®-3 devices, the default is not set to NONE so the device can achieve
a zero hold time.
• BOTH sets the delay ON for both the IBUF and IFD paths.
• IBUF sets the delay to OFF for any register inside the I/O component and to ON
for the registers outside of the component if the input buffer drives a register D pin
outside of the I/O component.
• IFD sets the delay to ON for any register inside the I/O component and to OFF for
the registers outside the component if a register occupies the input side of the I/O
component, regardless of whether the register has the IOB=TRUE constraint.
Applies to FPGA devices. Does not apply to CPLD devices.
Any I/O symbol (I/O pads, I/O buffers, or input pad nets)
Although IOBDELAY is attached to an I/O symbol, it applies to the entire I/O component.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to an I/O symbol
• Attribute Name: IOBDELAY
Constraints Guide
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