Xilinx Constraints Guide

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Chapter 1: Constraint Types Relative Location (RLOC) Constraints The RLOC constraint groups logic elements into discrete sets. • You can define the location of any element within the set relative to other elements in the set, regardless of eventual placement in the overall design. • For example, if RLOC constraints are applied to a group of eight flip-flops organized in a column, the mapper maintains the columnar order and moves the entire group of flip-flops as a single unit. • In contrast, absolute LOC constraints constrain design elements to specific locations on the FPGA die with no relation to other design elements. Placement Constraints • AREA_GROUP • BEL • LOC • LOCATE • Prohibit • RLOC • RLOC_ORIGIN • RLOC_RANGE • USE_RLOC Constraints Guide 16 www.xilinx.com UG625 (v. 13.2) July 6, 2011
Routing Directives Routing directives instruct PAR to perform specific operations. • AREA_GROUP • CONFIG_MODE • LOCK_PINS Chapter 1: Constraint Types Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 17
Page 1 and 2: Constraints Guide UG625 (v. 13.2) J
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: IBUF_DELAY_VALUE (Input Buffer Dela
Page 7 and 8: Constraint Types Attributes and Con
Page 9 and 10: Grouping Constraints for Timing Cha
Page 11 and 12: The name qualifier can include the
Page 13 and 14: Physical Constraints Mapping Note T
Page 15: Placement Constraints Chapter 1: Co
Page 19 and 20: Timing Constraints Chapter 1: Const
Page 21 and 22: UCF Timing Constraint Support From-
Page 23 and 24: Timing Model Constraint Priority Ch
Page 25 and 26: Chapter 2 Entry Strategies for Xili
Page 27 and 28: Constraint Schematic VHDL Verilog L
Page 29 and 30: An attribute can be declared in an
Page 31 and 32: User Constraints File (UCF) UCF Flo
Page 33 and 34: Syntax Chapter 2: Entry Strategies
Page 35 and 36: Entering Multiple Constraints File
Page 37 and 38: Chapter 2: Entry Strategies for Xil
Page 39 and 40: Running Constraints Editor As a Sta
Page 41 and 42: Defining I/O Pin Configurations Cha
Page 43 and 44: Placement LOC Constraint Assignment
Page 45 and 46: Verilog Example -------------module
Page 47 and 48: Chapter 2: Entry Strategies for Xil
Page 49 and 50: Timing Specification Priorities Cha
Page 51 and 52: Timing Constraint Strategies Chapte
Page 53 and 54: Chapter 3: Timing Constraint Strate
Page 55 and 56: The global OFFSET IN constraint for
Page 57 and 58: The PERIOD constraint syntax for th
Page 59 and 60: Example Chapter 3: Timing Constrain
Page 61 and 62: Chapter 3: Timing Constraint Strate
Page 63 and 64: The global OFFSET OUT constraints f
Page 65 and 66: Multi-Cycle Paths Chapter 3: Timing
Page 67 and 68:
Xilinx Constraints Each Xilinx® co
Page 69 and 70:
RANGE Chapter 4: Xilinx Constraints
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Chapter 4: Xilinx Constraints Range
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COMPRESSION GROUP PLACE Chapter 4:
Page 75 and 76:
Defining From Timing Groups Chapter
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BEL (BEL) The BEL (BEL) constraint:
Page 79 and 80:
BLKNM (Block Name) Architecture Sup
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BUFG (BUFG) The BUFG (BUFG) constra
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Clock Dedicated Route (CLOCK_DEDICA
Page 85 and 86:
COMPGRP (Component Group) Architect
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• S_SELECTMAP16 Slave SelectMAP M
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Verilog Syntax Chapter 4: Xilinx Co
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Page 93 and 94:
PCF Syntax CONFIG DCI_CASCADE = ",
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Default (DEFAULT) Chapter 4: Xilinx
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Example (* KEEPER = “TRUE” *) D
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DIFF_TERM (Diff_Term) Architecture
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DIRECTED_ROUTING (Directed Routing)
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DISABLE (Disable) The DISABLE (Disa
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DRIVE (Drive) The DRIVE (Drive) con
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XCF Syntax MODEL “entity_name”
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ENABLE (Enable) The ENABLE (Enable)
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ENABLE_SUSPEND (Enable Suspend) Arc
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Constraints Editor Syntax Chapter 4
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax NET “signal_na
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Chapter 4: Xilinx Constraints You a
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Page 125 and 126:
HBLKNM (Hierarchical Block Name) Ar
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HIODELAY_GROUP (HIODELAY Group) Arc
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Page 131 and 132:
HU_SET (HU Set) The HU_SET (HU Set)
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IBUF_DELAY_VALUE (Input Buffer Dela
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IFD_DELAY_VALUE (IFD Delay Value) T
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IN_TERM (In Term) Architecture Supp
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INREG (Input Registers) Architectur
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IOB (IOB) The IOB constraint: • I
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IOBDELAY (Input Output Block Delay)
Page 145 and 146:
IODELAY_GROUP (IODELAY Group) Limit
Page 147 and 148:
IOSTANDARD (Input Output Standard)
Page 149 and 150:
Pinout and Area Constraints Editor
Page 151 and 152:
Page 153 and 154:
Architecture Support Applicable Ele
Page 155 and 156:
Keeper (KEEPER) Architecture Suppor
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LOC (Location) The LOC (Location) c
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Chapter 4: Xilinx Constraints The w
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LOC Range Constraint Examples Const
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PlanAhead Syntax Chapter 4: Xilinx
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Schematic LOC=P17 Chapter 4: Xilinx
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Example One Chapter 4: Xilinx Const
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Slices Prohibited Example Two Chapt
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LOCK_PINS (Lock Pins) Architecture
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where value is any chosen name unde
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MAP (Map) Architecture Support Appl
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Specify the Verilog constraint as f
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Architecture Support Applicable Ele
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MAXDELAY (Maximum Delay) Architectu
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PCF Syntax item MAXDELAY = maxvalue
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MAXSKEW (Maximum Skew) The MAXSKEW
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FPGA Editor Syntax Chapter 4: Xilin
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MIODELAY_GROUP (MIODELAY Group) Arc
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Page 193 and 194:
UCF and NCF Syntax Chapter 4: Xilin
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where Chapter 4: Xilinx Constraints
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Falling Edge Constraints Chapter 4:
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PlanAhead Syntax Chapter 4: Xilinx
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where Chapter 4: Xilinx Constraints
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UCF Syntax NET “clock” TNM_NET
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Page 207 and 208:
Attribute OUT_TERM: string; Specify
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TIMESPEC PERIOD Method Chapter 4: X
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Examples of a Primary Clock with De
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where • period is the required cl
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New PERIOD Specifications Output Pi
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Post CRC (POST_CRC) Architecture Su
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Post CRC Frequency (POST_CRC_FREQ)
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Post CRC Signal (POST_CRC_SIGNAL) A
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PRIORITY (Priority) Architecture Su
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The following are not supported: Ch
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PULLDOWN (Pulldown) Architecture Su
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PULLUP (Pullup) Architecture Suppor
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PWR_MODE (Power Mode) Architecture
Page 233 and 234:
REG (Registers) The REG (Registers)
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RLOC (Relative Location) The Relati
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RLOC = X3Y4 Chapter 4: Xilinx Const
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Linking Sets Set Linkage Chapter 4:
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Chapter 4: Xilinx Constraints by th
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Linking Two HU_SET Sets Chapter 4:
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Specify the VHDL constraint as foll
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Chapter 4: Xilinx Constraints Diffe
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H_SET (H Set) Chapter 4: Xilinx Con
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Chapter 4: Xilinx Constraints The n
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Syntax Examples Chapter 4: Xilinx C
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RLOC_RANGE (Relative Location Range
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where the relative X values (m1 and
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UCF and NCF Syntax NET “mysignal
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VHDL Syntax Chapter 4: Xilinx Const
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SLOW (Slow) The SLOW (Slow) constra
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STEPPING (Stepping) Architecture Su
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VHDL Syntax Chapter 4: Xilinx Const
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Page 275 and 276:
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Chapter 4: Xilinx Constraints The f
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TIMEGRP (Timing Group) The TIMEGRP
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Defining Latch Subgroups by Gate Se
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Chapter 4: Xilinx Constraints When
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PCF Syntax TIMEGRP name; TIMEGRP na
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Separators FROM-TO Syntax TIMESPEC
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TNM (Timing Name) Chapter 4: Xilinx
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Chapter 4: Xilinx Constraints A qua
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
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Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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Page 309 and 310:
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Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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Xilinx Constraints Guide

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