Xilinx Constraints Guide

SLOW (Slow)
The SLOW (Slow) constraint:
• Is a basic fitter constraint
Architecture Support
Applicable Elements
• Enables the slew rate limited control
Applies to all FPGA devices and all CPLD devices.
• Output primitives
• Output pads
• Bidirectional pads
Propagation Rules
Chapter 4: Xilinx Constraints
You can also attach SLOW to the net connected to the pad component in a User
Constraints File (UCF). NGCBuild transfers SLOW from the net to the pad instance in
the Native Generic Database (NGD) file so that it can be processed by the mapper.
Use the following UCF syntax:
NET “net_name” SLOW;
SLOW is illegal when attached to a net except when the net is connected to a pad. In
this case, SLOW is treated as attached to the pad instance.
When attached to a design element, SLOW propagates to all applicable elements in
the hierarchy within the design element.
Syntax
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a valid instance
• Attribute Name
SLOW
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute SLOW : string;
Specify the VHDL constraint as follows:
attribute SLOW of {signal_name|entity_name} : {signal|entity} is “{TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
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