Xilinx Constraints Guide

Post CRC Signal (POST_CRC_SIGNAL)
Architecture Support
Applicable Elements
Propagation Rules
Chapter 4: Xilinx Constraints
Virtex®-5 devices support a configuration logic CRC error detection mode called
Post CRC Signal (POST_CRC_SIGNAL). In this mode, a pre-computed CRC for the
configuration bitstream is compared against a CRC computed by internal logic based on
periodic readback of the configuration memory cells. POST_CRC_SIGNAL determines
whether the INIT_B pin is enabled as an output for the SEU (Single Event Upset) error
signal. The error condition is still available from the FRAME_ECC_VIRTEX5 site. This
constraint is only applicable when POST_CRC is set to ENABLE.
Value Description
Values for POST_CRC_SIGNAL
FRAME_ECC_ONLY Disables the use of the INIT_B pin, with the FRAME_ECC site
as the sole source of the CRC error signal
INIT_AND_FRAME_ECC Leaves the INIT_B pin enabled as a source of the CRC error
signal (default)
Applies to Virtex®-5 devices only.
Applies to the entire device and is not specified on any particular design element.
Applies to the entire design.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF Syntax
CONFIG POST_CRC_SIGNAL = [FRAME_ECC_ONLY|INIT_AND_FRAME_ECC];
PCF Syntax
CONFIG POST_CRC_SIGNAL = [FRAME_ECC_ONLY|INIT_AND_FRAME_ECC];
Constraints Guide
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