Xilinx Constraints Guide

MAXSKEW (Maximum Skew)
The MAXSKEW (Maximum Skew) constraint:
• Is a timing constraint
Architecture Support
Applicable Elements
• Is used to control the maximum amount of skew on a net.
Chapter 4: Xilinx Constraints
• Is commonly used to control the skew of local clocks, or clocks that are not on the
global clock network.
• Is not necessary, and is not recommended, for global clock networks.
Skew is the difference between the delays of all loads driven by the net. Because the
constraint identifies all loads driven by the net, skew may be reported between loads
that have no logical connection. You can control the maximum allowable skew on a net
by attaching MAXSKEW directly to the net.
To understand what MAXSKEW defines, consider the following example.
In the preceding diagram, for ta(2), 2 ns is the maximum delay for the Register A clock.
For tb(4), 4 ns is the maximum delay for the Register B clock. MAXSKEW defines the
maximum of tb minus the maximum of ta, that is, 4-2=2.
In some cases, relative minimum delays are used on a net for setup and hold timing
analysis. When MAXSKEW is applied to network resources which use relative
minimum delays, MAXSKEW takes relative minimum delays into account in the
calculation of skew.
Overuse of MAXSKEW, or too tight of a requirement (value), can cause long PAR
runtimes.
Applies to FPGA devices. Does not apply to CPLD devices.
Nets
Propagation Rules
Applies to the net to which it is attached.
yntax
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Constraints Guide
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