Xilinx Constraints Guide

Chapter 2: Entry Strategies for Xilinx Constraints
Constraint Schematic
VHDL
Verilog
NCF UCF Constraints
Editor
PCF XCF Plan-
Ahead
TIMEGRP Yes Yes Yes Yes Yes Yes
TIMESPEC Yes Yes Yes Yes Yes
TNM Yes Yes Yes Yes Yes
TNM_NET Yes Yes Yes Yes Yes Yes
TPSYNC Yes Yes Yes
TPTHRU Yes Yes Yes Yes
PACE FPGA
Editor
TSidentifier Yes Yes Yes Yes Yes Yes
U_SET Yes Yes Yes Yes Yes
USE_RLOC Yes Yes Yes Yes Yes Yes
VCCAUX Yes Yes
VCCAUX_IO Yes Yes Yes Yes
VOLTAGE Yes Yes Yes Yes
VREF Yes Yes Yes
WIREAND Yes Yes Yes Yes
XBLKNM Yes Yes Yes Yes Yes
Schematic Design
VHDL Attributes
ISE®
Design
Suite
Follow these rules to add Xilinx® constraints as attributes within a symbol or schematic
drawing:
• If a constraint applies to a net, add it as an attribute to the net.
• If a constraint applies to an instance, add it as an attribute to the instance.
• You cannot add global constraints such as PART and PROHIBIT.
• You cannot add any timing specifications that would be attached to a TIMESPEC
or TIMEGRP.
• Enter attribute names and values in either all uppercase or all lowercase. Mixed
uppercase and lowercase is not allowed.
For more information about creating, modifying, and displaying attributes, see the
Schematic and Symbol Editors Help.
The syntax for any constraint that can be entered in a schematic is described in the
section for that constraint. For an example of correct schematic syntax, see the Schematic
Syntax Example in BEL.
In VHDL code, constraints can be specified with VHDL attributes. Before it can be used,
a constraint must be declared with the following syntax:
attribute attribute_name : string;
Example
attribute RLOC : string;
Constraints Guide
28 www.xilinx.com UG625 (v. 13.2) July 6, 2011