Xilinx Constraints Guide

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Chapter 4: Xilinx Constraints VHDL Syntax Declare the VHDL constraint as follows: attribute iobdelay: string; Specify the VHDL constraint as follows: attribute iobdelay of {component_name |label_name}: {component|label} is “{NONE|BOTH|IBUF|IFD}”; For more information about basic VHDL syntax, see VHDL Attributes. Verilog Syntax Place the Verilog constraint immediately before the module or instantiation. Specify the Verilog constraint as follows: (* IOBDELAY = {NONE|BOTH|IBUF|IFD} *) For more information on basic Verilog syntax, see Verilog Attributes. UCF and NCF Syntax INST “ instance_name” IOBDELAY={NONE|BOTH|IBUF|IFD}; Constraints Guide 144 www.xilinx.com UG625 (v. 13.2) July 6, 2011
IODELAY_GROUP (IODELAY Group) Limitations with LOC Architecture Support Applicable Elements Propagation Rules The IODELAY_GROUP (IODELAY Group) constraint: • Is a design implementation constraint. Chapter 4: Xilinx Constraints • Groups a set of IDELAY and IODELAY constraints with an IDELAYCTRL to enable automatic replication and placement of IDELAYCTRL in a design. For more information, see the IDELAYCTRL section of the appropriate device user guide. • Use IODELAY_GROUP only when replicating a single IDELAYCTRL to multiple banks, without a LOC constraint. • Do not use IODELAY_GROUP in conjunction with IDELAYCTRL instances that have a LOC constraint. • Instantiate only one IDELAYCTRL in the design. • Do not apply a LOC constraint. • Group any IODELAY constraint that needs an IDELAYCTRL into an IODELAY_GROUP. • Create one group for each bank. Applies to Virtex®-4, Virtex-5, Virtex-6, and 7 series devices. • For Virtex-4 devices, IODELAY_GROUP is supported only when using the Timing Driven Pack and Placement Option in MAP. • While IODELAY_GROUP is supported on Virtex-4 and Virtex-5 devices, it is not the recommended method for replicating IDELAYCTRL. For the recommended method, see the appropriate device user guide. • IODELAY_GROUP is the recommended method for replicating IDELAYCTRL primitives on Virtex-6 and 7 series devices. IDELAY, IODELAY, IODELAYE1, IDELAYE2, ODELAYE2 and IDELAYCTRL IODELAY_GROUP can only be attached to a design element. It is illegal to attach IODELAY_GROUP to a net, signal, or pin. To merge two or more embedded IODELAY_GROUP constraints in your design, see MIODELAY_GROUP. Syntax Examples The following examples show how to use this constraint with particular tools or methods. If a tool or method is not listed, you cannot use this constraint with it. VHDL Syntax Declare the VHDL constraint as follows: attribute IODELAY_GROUP: string; Specify the VHDL constraint as follows: attribute IODELAY_GROUP of {component_name|label_name}: {component|label} is "group_name"; Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 145
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Constraints Guide UG625 (v. 13.2) J
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Table of Contents Revision History
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IBUF_DELAY_VALUE (Input Buffer Dela
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Constraint Types Attributes and Con
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Grouping Constraints for Timing Cha
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The name qualifier can include the
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Physical Constraints Mapping Note T
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Placement Constraints Chapter 1: Co
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Routing Directives Routing directiv
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Timing Constraints Chapter 1: Const
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UCF Timing Constraint Support From-
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Timing Model Constraint Priority Ch
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Chapter 2 Entry Strategies for Xili
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Constraint Schematic VHDL Verilog L
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An attribute can be declared in an
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User Constraints File (UCF) UCF Flo
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Syntax Chapter 2: Entry Strategies
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Entering Multiple Constraints File
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Chapter 2: Entry Strategies for Xil
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Running Constraints Editor As a Sta
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Defining I/O Pin Configurations Cha
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Placement LOC Constraint Assignment
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Verilog Example -------------module
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Chapter 2: Entry Strategies for Xil
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Timing Specification Priorities Cha
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Timing Constraint Strategies Chapte
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Chapter 3: Timing Constraint Strate
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The global OFFSET IN constraint for
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The PERIOD constraint syntax for th
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Example Chapter 3: Timing Constrain
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Chapter 3: Timing Constraint Strate
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The global OFFSET OUT constraints f
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Multi-Cycle Paths Chapter 3: Timing
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Xilinx Constraints Each Xilinx® co
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RANGE Chapter 4: Xilinx Constraints
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Chapter 4: Xilinx Constraints Range
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COMPRESSION GROUP PLACE Chapter 4:
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Defining From Timing Groups Chapter
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BEL (BEL) The BEL (BEL) constraint:
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BLKNM (Block Name) Architecture Sup
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BUFG (BUFG) The BUFG (BUFG) constra
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Clock Dedicated Route (CLOCK_DEDICA
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COMPGRP (Component Group) Architect
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• S_SELECTMAP16 Slave SelectMAP M
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Verilog Syntax Chapter 4: Xilinx Co
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Page 93 and 94: PCF Syntax CONFIG DCI_CASCADE = ",
Page 95 and 96: Default (DEFAULT) Chapter 4: Xilinx
Page 97 and 98: Example (* KEEPER = “TRUE” *) D
Page 99 and 100: DIFF_TERM (Diff_Term) Architecture
Page 101 and 102: DIRECTED_ROUTING (Directed Routing)
Page 103 and 104: DISABLE (Disable) The DISABLE (Disa
Page 105 and 106: DRIVE (Drive) The DRIVE (Drive) con
Page 107 and 108: XCF Syntax MODEL “entity_name”
Page 109 and 110: ENABLE (Enable) The ENABLE (Enable)
Page 111 and 112: ENABLE_SUSPEND (Enable Suspend) Arc
Page 113 and 114: Verilog Syntax Chapter 4: Xilinx Co
Page 115 and 116: Constraints Editor Syntax Chapter 4
Page 117 and 118: VHDL Syntax Declare the VHDL constr
Page 119 and 120: UCF and NCF Syntax NET “signal_na
Page 121 and 122: Chapter 4: Xilinx Constraints You a
Page 123 and 124: Constraints Editor Syntax Chapter 4
Page 125 and 126: HBLKNM (Hierarchical Block Name) Ar
Page 127 and 128: HIODELAY_GROUP (HIODELAY Group) Arc
Page 131 and 132: HU_SET (HU Set) The HU_SET (HU Set)
Page 133 and 134: IBUF_DELAY_VALUE (Input Buffer Dela
Page 135 and 136: IFD_DELAY_VALUE (IFD Delay Value) T
Page 137 and 138: IN_TERM (In Term) Architecture Supp
Page 139 and 140: INREG (Input Registers) Architectur
Page 141 and 142: IOB (IOB) The IOB constraint: • I
Page 143: IOBDELAY (Input Output Block Delay)
Page 147 and 148: IOSTANDARD (Input Output Standard)
Page 149 and 150: Pinout and Area Constraints Editor
Page 151 and 152: Verilog Syntax Chapter 4: Xilinx Co
Page 153 and 154: Architecture Support Applicable Ele
Page 155 and 156: Keeper (KEEPER) Architecture Suppor
Page 157 and 158: LOC (Location) The LOC (Location) c
Page 159 and 160: Chapter 4: Xilinx Constraints The w
Page 161 and 162: LOC Range Constraint Examples Const
Page 163 and 164: PlanAhead Syntax Chapter 4: Xilinx
Page 165 and 166: Schematic LOC=P17 Chapter 4: Xilinx
Page 167 and 168: Example One Chapter 4: Xilinx Const
Page 169 and 170: Slices Prohibited Example Two Chapt
Page 171 and 172: LOCK_PINS (Lock Pins) Architecture
Page 173 and 174: where value is any chosen name unde
Page 175 and 176: MAP (Map) Architecture Support Appl
Page 177 and 178: Specify the Verilog constraint as f
Page 179 and 180: Architecture Support Applicable Ele
Page 181 and 182: MAXDELAY (Maximum Delay) Architectu
Page 183 and 184: PCF Syntax item MAXDELAY = maxvalue
Page 185 and 186: MAXSKEW (Maximum Skew) The MAXSKEW
Page 187 and 188: FPGA Editor Syntax Chapter 4: Xilin
Page 189 and 190: MIODELAY_GROUP (MIODELAY Group) Arc
Page 193 and 194: UCF and NCF Syntax Chapter 4: Xilin
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where Chapter 4: Xilinx Constraints
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Falling Edge Constraints Chapter 4:
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PlanAhead Syntax Chapter 4: Xilinx
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where Chapter 4: Xilinx Constraints
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UCF Syntax NET “clock” TNM_NET
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Attribute OUT_TERM: string; Specify
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TIMESPEC PERIOD Method Chapter 4: X
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Examples of a Primary Clock with De
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where • period is the required cl
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New PERIOD Specifications Output Pi
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Post CRC (POST_CRC) Architecture Su
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Post CRC Frequency (POST_CRC_FREQ)
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Post CRC Signal (POST_CRC_SIGNAL) A
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PRIORITY (Priority) Architecture Su
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The following are not supported: Ch
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PULLDOWN (Pulldown) Architecture Su
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PULLUP (Pullup) Architecture Suppor
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PWR_MODE (Power Mode) Architecture
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REG (Registers) The REG (Registers)
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RLOC (Relative Location) The Relati
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RLOC = X3Y4 Chapter 4: Xilinx Const
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Linking Sets Set Linkage Chapter 4:
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Chapter 4: Xilinx Constraints by th
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Linking Two HU_SET Sets Chapter 4:
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Specify the VHDL constraint as foll
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Chapter 4: Xilinx Constraints Diffe
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H_SET (H Set) Chapter 4: Xilinx Con
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Chapter 4: Xilinx Constraints The n
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Syntax Examples Chapter 4: Xilinx C
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RLOC_RANGE (Relative Location Range
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where the relative X values (m1 and
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax NET “mysignal
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VHDL Syntax Chapter 4: Xilinx Const
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SLOW (Slow) The SLOW (Slow) constra
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STEPPING (Stepping) Architecture Su
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VHDL Syntax Chapter 4: Xilinx Const
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Constraints Editor Syntax Chapter 4
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Chapter 4: Xilinx Constraints The f
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TIMEGRP (Timing Group) The TIMEGRP
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Defining Latch Subgroups by Gate Se
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Chapter 4: Xilinx Constraints When
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PCF Syntax TIMEGRP name; TIMEGRP na
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Separators FROM-TO Syntax TIMESPEC
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TNM (Timing Name) Chapter 4: Xilinx
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Chapter 4: Xilinx Constraints A qua
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
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Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax Chapter 4: Xilin
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Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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UCF and NCF Syntax Chapter 4: Xilin
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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