Xilinx Constraints Guide

TIMESPEC PERIOD Method
Chapter 4: Xilinx Constraints
The primary, recommended method for defining a clock period allows more complex
derivative relationships to be defined as well as a simple clock period. The following
constraint is defined using the TIMESPEC keyword in conjunction with a TNM
constraint attached to the relevant clock net.
UCF Syntax
TIMESPEC “TSidentifier”=PERIOD “TNM_reference” period {HIGH | LOW}
[high_or_low_time] INPUT_JITTER value;
where
• identifier is a reference identifier that has a unique name
• TNM_reference identifies the group of elements to which the period constraint
applies. This is typically the name of a TNM_NET that was attached to a clock
net, but it can be any TNM group or user group (TIMEGRP) that contains only
synchronous elements.
The following rules apply:
• The variable name period is the required clock period.
• The default units for period are nanoseconds, but the number can be followed by
ps, ns, micro, or ms. The period can also be specified as a frequency value, using
units of MHz, GHz, or kHZ.
• Units may be entered with or without a leading space.
• Units are case-insensitive.
• The HIGH|LOW keyword indicates whether the first pulse in the period is
high or low, and the optional high_or_low_time is the polarity of the first pulse.
This defines the initial clock edge and is used in the OFFSET constraint. HIGH
is the default logic level if the logic level is not specified.
• If an actual time is specified, it must be less than the period.
• If no high_or_low_time is specified the default duty cycle is 50%.
• The default units for high_or_low_time is ns, but the number can be followed by
% or by ps, ns, micro, or ms to specify an actual time measurement.
• INPUT_JITTER is the random, peak-to-peak jitter on an input clock. The default
units are picoseconds.
Examples
Clock net sys_clk has the constraint tnm=master_clk attached to it and the following
constraint is attached to TIMESPEC.
UCF Syntax
TIMESPEC TS_master = PERIOD “master_clk” 50 HIGH 30 INPUT_JITTER 50;
This period constraint applies to the net master_clk, and defines a clock period of 50
nanoseconds, with an initial 30 nanosecond high time, and INPUT_JITTER at 50 ps.
TIMESPEC TS_clkinA = PERIOD “clkinA” 21 ns LOW 50% INPUT_JITTER 500
ps; TIMESPEC TS_clkinB = PERIOD “clkinB” 21 ns HIGH 50% INPUT_JITTER
500 ps;
NET PERIOD Method
Caution! This is a secondary method, and is not recommended.
Another method of defining a clock period is to attach the following constraint directly
to a net in the path that drives the register clock pins.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 209