Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
U SET (U_SET)
Architecture Support
Applicable Elements
The U_SET (U SET) constraint:
• Is an advanced mapping constraint.
• Groups design elements with attached RLOC constraints that are distributed
throughout the design hierarchy into a single set.
The elements that are members of a U_SET can cross the design hierarchy. You can
arbitrarily select objects without regard to the design hierarchy and tag them as
members of a U_SET. For more information, see RLOC Sets.
Applies to FPGA devices. Does not apply to CPLD devices.
This constraint may be used with an FPGA device in one or more of the following design
elements, or categories of design elements. Not all devices support all elements. To see
which design elements can be used with which devices, see the Libraries Guides. For
more information, see the device data sheet.
• Registers
• Macro Instance
• FMAP
• ROM
• RAMS
• RAMD
• BUFT
• MULT18X18S
• RAMB4_Sm_Sn
• RAMB4_Sn
• RAMB16_Sm_Sn
• RAMB16_Sn
• RAMB16
• DSP48
Propagation Rules
This constraint is a macro constraint. Any attachment to a net is illegal.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a valid instance
• Attribute Name: U_SET
• Attribute Values: name
where
name is the identifier of the set
Constraints Guide
306 www.xilinx.com UG625 (v. 13.2) July 6, 2011