Xilinx Constraints Guide

PULLUP (Pullup)
Architecture Support
Applicable Elements
The PULLUP (Pullup) constraint:
• Is a basic mapping constraint.
Chapter 4: Xilinx Constraints
• Guarantees a logic High level to allow tri-stated nets to avoid floating when not
being driven.
KEEPER, PULLUP, and PULLDOWN are only valid on pad NET, not on INST of any
kind.
For CoolRunner-II designs, KEEPER and PULLUP are mutually exclusive across
the whole device.
NGDBUILD ignores the following:
• DEFAULT KEEPER = FALSE
• DEFAULT PULLUP = FALSE
• DEFAULT PULLDOWN = FALSE
Applies to all FPGA devices and the CoolRunner XPLA3 and CoolRunner-II CPLD
devices.
• Input
• Tristate outputs
Propagation Rules
• Bidirectional pad nets
This constraint is a net constraint. Any attachment to a design element is illegal.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a pad net
• Attribute Name
PULLUP
• Attribute Values
TRUE
FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute PULLUP: string;
Specify the VHDL constraint as follows:
attribute PULLUP of signal_name: signal is “{YES|NO|TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 229