Xilinx Constraints Guide

Specify the VHDL constraint as follows:
Chapter 4: Xilinx Constraints
attribute rloc of {component_name|entity_name| label_name}: {component |entity|label}
is “[element]X mYn[ .extension]”;
For descriptions of valid values, see Guidelines for Specifying Relative Locations.
For more information about basic VHDL syntax, see VHDL Attributes.
The following code sample shows how to use RLOCs with a VHDL generate statement.
The code is a simple example showing how to auto-generate the RLOCs for several
instantiated FDEs. This methodology can be used with virtually any primitive.
Note The user must create the itoa function.
LEN:for i in 0 to bits-1 generate
constant row :natural:=((width-1)/2)-(i/2);
constant column:natural:=0;
constant slice:natural:=0;
constant rloc_str : string := "R" & itoa(row) & "C" & itoa(column) & ".S" & itoa(slice);
attribute RLOC of U1: label is rloc_str;
begin
U1: FDE port map (
Q=> dd(j),
D=> ff_d,
C=> clk,
CE =>lcl_en(en_idx));
end generate LEN;
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* RLOC = “[element ]XmY n[.extension ]” *)
For descriptions of valid value, see Guidelines for Specifying Relative Locations in
this chapter.
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
For all FPGA devices, the following statement specifies that an instantiation of FF1 be
placed in a slice that is +4 X coordinates and +4 Y coordinates relative to the origin slice.
INST “/V2/design/FF1” RLOC=X4Y4;
XCF Syntax
For Virtex®-4 and Virtex-5 devices:
BEGIN MODEL “entity_name ”
INST "instance_name " rloc=[element]XmYn [.extension] ;
END;
PlanAhead Syntax
For more information about using the PlanAhead software to create constraints, see
Floorplanning the Design in the PlanAhead User Guide (UG632). See PlanAhead in this
Guide for information about:
• Defining placement constraints
• Assigning placement constraints
• Defining I/O pin configurations
• Floorplanning and placement constraints
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 245