Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
For a description of group_name, see the UCF Syntax for this constraint.
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* IODELAY_GROUP = "group_name" *)
For a description of group_name, see UCF Syntax below.
For more information about basic Verilog syntax, see Verilog Attributes.
UCF Syntax
INST "instance_name" IODELAY_GROUP = group_name;
where
group_name is the name assigned to a set of IDELAY or IODELAY constraints and an
IDELAYCTRL to uniquely define the group.
Constraints Guide
146 www.xilinx.com UG625 (v. 13.2) July 6, 2011