Xilinx Constraints Guide

INREG (Input Registers)
Architecture Support
Applicable Elements
Propagation Rules
Chapter 4: Xilinx Constraints
INREG (Input Registers) applies to register and latch instances with their D-inputs
driven by input pads, or to the Q-output nets of such registers and latches. By default,
registers and latches for CoolRunner XPLA3 and CoolRunner-II designs that have
their D-inputs driven by input pads are automatically implemented using the device’s
Fast Input path, where possible. If you disable the ISE® Design Suite property Use Fast
Input for INREG for the Fit (Implement Design) process, then only register and latches
with the INREG attribute are considered for Fast Input optimization.
Applies to CoolRunner XPLA3 and CoolRunner-II devices only.
Applies to register and latch instances with their D-inputs driven by input pads or to the
Q-output nets of such registers or latches.
Applies to register or latch to which it is attached or to the Q-output nets of such
registers or latches
Syntax Excamples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a register, latch, or net
• Attribute Name
INREG
• Attribute Values
None (TRUE by default)
UCF Syntax
NET “signal_name” INREG;
INST “register_name” INREG;
Constraints Guide
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