Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
VCCAUX_IO
Architecture Support
Applicable Elements
Propagation Rules
Syntax
The auxiliary I/O (VCCAUX_IO) supply rail is specific to the HP I/O banks only. It is
used to power some of the I/O circuitry in the HP bank, including the single-ended and
differential input buffer circuits. HP I/O banks contain both VCCAUX_IO pins, as well
as the "regular" VCCAUX pins which power the various internal block features. Inside
the 7 series device packages, the VCCAUX_IO pins are connected together in groups
of three to four I/O banks. The number of I/O banks that have their VCCAUX_IO pins
grouped together depends on the particular 7 series part and package combination. See
the 7 Series Packaging and Pinout Guide for banks that are grouped together for each part
and package combination. The VCCAUX and VCCAUX_IO supplies must turn on
before the VCCO supply. See the 7 Series FPGA Data Sheet for more details regarding
power supply requirements.
Applies to Kintex-7 and Virtex®-7 devices
See the SelectIO User Guide.
See the SelectIO User Guide.
The following sections show the syntax for this constraint.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
Attribute Name: VCCAUX_IO
VHDL Syntax
Declare the VHDL constraint as follows:
attribute VCCAUX_IO: string;
Specify the VHDL constraint as follows:
attribute VCCAUX_IO of {component_name |label_name}: {component|label} is
“{NORMAL|HIGH|DONTCARE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* VCCAUX_IO = { NORMAL|HIGH|DONTCARE} *)
For more information about basic Verilog syntax, see Verilog Attributes.
Constraints Guide
318 www.xilinx.com UG625 (v. 13.2) July 6, 2011