Xilinx Constraints Guide

Chapter 2: Entry Strategies for Xilinx Constraints
Setting Constraints in PACE
For CPLD devices, you can set constraints in the Pinout and Area Constraints Editor
(PACE). The Pin Assignments Editor in PACE is used to:
• Assign location constraints to IOs.
• Assign IO properties such as IO Standards.
For a list of the constraints and devices with which PACE can be used, see Constraints
Entry Methods. For more information about accessing and using PACE, see the ISE®
Design Suite Help.
Partial Design Pin Preassignment
This section deals with Pin Preassignment when a design is partially completed. For
information on Pin Preassignment in which a Hardware Description Language (HDL)
template is built by adding constraints to pins that are defined within PlanAhead
or PACE, see the ISE® Design Suite Help. PACE is supported for CPLD devices.
PlanAhead is supported for FPGA devices.
Designs that are not yet fully coded might still have layout requirements. Pin
assignments, voltage standards, banking rules, and other board requirements might be
in place long before the design has reached the point where these constraints can be
applied. Pin Preassignment allows the design pinout rules to be determined before the
design logic has been completed.
To use Pin Preassignment in PlanAhead or PACE:
1. Provide the complete list of ports in your top-level design
2. Assign I/O constraints to them
Even if the ports are not used by any logic (that is, no loads for input pins, no sources for
output pins), they can still receive constraints and be kept through implementation.
Assign Location (LOC) or Input Output Standard (IOSTANDARD) constraints in the
User Constraints File (UCF) just like for any I/O pin. These requirements are annotated
in the database. PlanAhead and PACE can be used to assign pin locations, banking
groups or voltage standards, and DRC checks can be run. The final PAD report contains
any pins that have logic or constraints associated with them.
This implementation is incomplete and cannot be downloaded to the hardware. You
should expect these errors during the DRC phase of bitstream generation (BitGen):
• ERROR: PhysDesignRules:368 - The signal is incomplete. The signal is
not driven by any source pin in the design.
• ERROR: PhysDesignRules:10 - The network is completely unrouted.
To trim any unused ports from the design, remove the associated constraints. The
Translate (NGDBuild) phase trims these unused pins.
In this example, there are six top-level ports. Only three (clk, A, C) are currently used.
Of the remaining three ports:
• B is kept because it has a Location (LOC) constraint.
• D is kept because it has an Input Output Standard (IOSTANDARD) constraint.
• E is trimmed because it is completely unused and unconstrained.
Constraints Guide
44 www.xilinx.com UG625 (v. 13.2) July 6, 2011