Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
PROHIBIT (Prohibit)
The PROHIBIT (Prohibit) constraint:
• Is a basic placement constraint.
• Disallows the use of a site within PAR, FPGA Editor, and the CPLD fitter.
For an FPGA device, use the following location types to define the physical location
of an element.
Location Types for FPGA Devices
Element Type Location Specification Meaning
IOB P12 IOB location (chip carrier)
A12 IOB location (pin grid)
T, B, L, R Applies to IOBs and indicates edge
locations (bottom, left, top, right) for
Spartan®-3, Spartan-3A, Spartan-3E,
Virtex®-4 and Virtex-5 devices
LB, RB, LT, RT, BR, TR, BL, TL Applies to IOBs and indicates half
edges (for example, left bottom, right
bottom) for Spartan-3, Spartan-3A,
Spartan-3E, Virtex-4 and Virtex-5
devices
Bank 0, Bank 1, Bank 2, Bank 3, Bank 4,
Bank 5, Bank 6, Bank 7
Applies to IOBs and indicates
half edges (banks) for Spartan-3,
Spartan-3A, Spartan-3E, Virtex-4 and
Virtex-5 devices
Slice SLICE_X22Y3 Slice location for Spartan-3, Spartan-3A,
Spartan-3E, Virtex-4 and Virtex-5
devices
block RAM RAMB16_X2Y56 Block RAM location for Spartan-3,
Spartan-3A, Spartan-3E, Virtex-4 and
Virtex-5 devices
Multiplier MULT18X18_X55Y82 Multiplier location for Spartan-3,
Spartan-3A, Spartan-3E, Virtex-4 and
Virtex-5 devices
Global Clock BUFGMUX0P Global clock buffer location for
Spartan-3, Spartan-3A, Spartan-3E,
Virtex-4 and Virtex-5 devices
Digital Clock Manager (DCM) DCM_X[A]Y[B] Digital Clock Manager for Spartan-3,
Spartan-3A, Spartan-3E, Virtex-4 and
Virtex-5 devices
Phase Lock Loop (PLL) PLL_X[A]Y[B] Phase Lock Loop for Spartan-3,
Spartan-3A, Spartan-3E, Virtex-4 and
Virtex-5 devices
Mixed-Mode Clock Manager
(MMCM)
MMCM_X[A]Y[B] Mixed-Mode Clock Manager for
Virtex-6
You can use the wildcard character (*) to replace a single location with a range as shown
in the following example.
SLICE_X*Y5
Any slice of an FPGA device whose Y-coordinate is 5
Constraints Guide
224 www.xilinx.com UG625 (v. 13.2) July 6, 2011