Xilinx Constraints Guide

Chapter 1: Constraint Types
Independent of the way timing constraints are specified, the Clock Signal option affects
timing constraint processing. In the case where a clock signal goes through which input
pin is the real clock pin. The CLOCK_SIGNAL constraint allows you to define the clock
pin. See the XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices
(UG627) for more information.
Applying XST Timing Constraints
You can apply XST timing constraints by means of:
• The -glob_opt command line switch, OR
• The XST Constraint File (XCF)
Command Line Switch
• Using the -glob_opt command line switch is the same as selecting Process
Properties > Synthesis Options > Global Optimization Goal.
• Using -glob_opt allows you to apply global timing constraints to the entire design.
• You cannot specify a value for these constraints.
• XST optimizes them for the best performance.
• These constraints are overridden by constraints specified in the XCF.
XST Constraint File (XCF)
Using the XCF allows you to use the native UCF timing constraint syntax. Using the
XCF syntax, XST supports constraints such as:
• TNM_NET
• TIMEGRP
• PERIOD
• TIG
• FROM-TO
You can use both wildcards and hierarchical names.
Timing constraints are not written to the NGC file by default. Timing constraints are
written to the NGC file only when:
• Write Timing Constraints is checked in ISE® Design Suite in Process > Properties or
• -write_timing_constraints option is specified in the command line.
Constraints Guide
20 www.xilinx.com UG625 (v. 13.2) July 6, 2011