Xilinx Constraints Guide

Keeper (KEEPER)
Architecture Support
Applicable Elements
Propagation Rules
The Keeper (KEEPER) constraint:
• Is a basic mapping constraint.
• Retains the value of the output net to which it is attached.
Chapter 4: Xilinx Constraints
For example, if logic 1 is being driven onto the net, KEEPER drives a weak/resistive
1 onto the net. If the net driver is then tristated, KEEPER continues to drive a
weak/resistive 1 onto the net.
The KEEPER constraint must follow the same banking rules as the KEEPER component.
For more information on banking rules, see the Xilinx® Libraries Guides.
KEEPER, PULLUP, and PULLDOWN are valid only on pad NETs, not on INSTs of
any kind.
For CoolRunner-II devices, the use of KEEPER and the use of PULLUP are mutually
exclusive across the whole device.
Applies to all FPGA devices and CoolRunner-II CPLD devices.
Tristate input/output pad nets
KEEPER is illegal when attached to a net or signal except when the net or signal is
connected to a pad. In this case, KEEPER is treated as attached to the pad instance.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to an output pad net
• Attribute Name
KEEPER
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute keeper: string;
Specify the VHDL constraint as follows:
attribute keeper of signal_name : signal is “{YES|NO|TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
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