Xilinx Constraints Guide

VREF (VREF)
The VREF (VREF) constraint:
Architecture Support
Applicable Elements
Propagation Rules
Chapter 4: Xilinx Constraints
• Applies to the design as a global attribute (not directly applicable to any element
in the design).
• Configures listed pins as VREF supply pins to be used in conjunction with other I/O
pins designated with one of the SSTL or HSTL I/O Standards.
Because VREF is selectable on any I/O in CoolRunner-II designs, it allows you to select
which pins are VREF pins. Double-check pin assignment in the report (RPT) file. If you
do not specify any VREF pins for the differential I/O standards, HSTL and SSTL, or if
you do not specify sufficient VREF pins within the required proximity of differential
I/O pins, the fitter automatically assigns sufficient VREF.
Applies only to CoolRunner-II devices with 128 macrocells and larger.
Applies globally to the entire design.
Configures listed pins as VREF supply pins to be used in conjunction with other I/O pins
designated with one of the SSTL or HSTL I/O Standards.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Values
• Pnn
• rc
where
nn is a numeric pin number
where
– r=alphabetic row
– c=numeric column
Schematic Syntax
VREF=value_list (on CONFIG symbol)
UCF and NCF Syntax
CONFIG VREF=value_list;
CONFIG VREF=P12,P13;
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 321