Xilinx Constraints Guide

Placement LOC Constraint Assignment
Chapter 2: Entry Strategies for Xilinx Constraints
The PlanAhead software enables you to lock down any logic to specific device sites. This
often includes global logic objects such as the following: BUFG, BRAM, MULT, PPC405,
GT, DLL, and DCM.
You can place logic objects by simply dragging the desired logic object from any of the
appropriate PlanAhead software views and drop it in the Device View in the Workspace.
Some types of logic such as I/O ports enable you to enter the desired location site in the
object General Properties view.
For more information about assigning placement constraints, see “Using Placement
Constraints” in the “Floorplanning the Design” chapter of the PlanAhead User Guide
(UG632).
Area Group Assignment
Area groups are the primary means of placing logic in specific regions of the device, for
example, within a particular clock region. The PlanAhead software enables you to create
area groups using a wide variety of methods. Assistance with connectivity, size logic
types and ranges are all provided by the tool including DRCs to ensure proper Area
Group (AREA_GROUP) property definition.
For more information about creating area group constraints, see Floorplanning the Design
in the PlanAhead User Guide (UG632).
Constraints Guide
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