Xilinx Constraints Guide

MAXDELAY (Maximum Delay)
Architecture Support
Applicable Elements
Propagation Rules
Chapter 4: Xilinx Constraints
MAXDELAY (Maximum Delay) defines the maximum allowable delay on a net.
Applies to FPGA devices. Does not apply to CPLD devices.
Applies to the net to which it is attached.
Applies to the net to which it is attached
Syntax
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a net
• Attribute Name: MAXDELAY
• Attribute Values: value units
where
value is the numerical time delay
units are:
– micro
– ms
– ns
– ps
VHDL Syntax
Declare the VHDL constraint as follows:
attribute maxdelay: string;
Specify the VHDL constraint as follows:
attribute maxdelay of signal_name: signal is “value [units]”;
where
• value is any positive integer
• units are:
– ps
– ns (default)
– micro
– ms
– GHz
– MHz
– kHz
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 181