Xilinx Constraints Guide

Chapter 3: Timing Constraint Strategies
Source Synchronous Inputs
The source synchronous interface is an interface in which a clock is regenerated and
transmitted along with the data from the source device. This clock is then used to
capture the data in the FPGA device. A simplified Source Synchronous interface with
associated DDR timing is shown in the following diagram.
Because this interface uses a regenerated clock that is transmitted along the same board
traces as the data, the board trace delays and skew no longer limit the operating
frequency of the interface. The higher frequency also results in the source synchronous
input interface typically being a dual data rate (DDR) application. In this source
synchronous DDR application example, unique data is transmitted from the source
device on both the rising and falling clock edges and captured in the FPGA using the
regenerated clock.
Using OFFSET IN is the most efficient way to specify the input timing for a source
synchronous interface. In the DDR interface, one OFFSET IN constraint is defined for
each edge of the input interface clock. These constraints will cover the paths of all input
data bits that are captured in registers triggered by the specified input clock edge.
To specify the input timing:
1. Specify the clock PERIOD constraint for the input clock associated with the interface.
2. Define the global OFFSET IN constraint for the rising edge of the interface.
3. Define the global OFFSET IN constraint for the falling edge of the interface.
Timing Diagram for Ideal Source Synchronous DDR Interface Example
The following example shows a timing diagram for an ideal Source Synchronous DDR
interface. The interface has a clock period of 5 ns with a 50/50 duty cycle, and the data
for both bits of the bus remains valid for the entire ½ period.
Constraints Guide
54 www.xilinx.com UG625 (v. 13.2) July 6, 2011