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Suprem-III User´s Manual
49. Example 1: NMOS Silicon Gate.
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Presented here is an example of the simulation of a NMOS silicon gate process. Three vertical cross-sections
are simulated, one through the center of the gate region, the second through the source or drain region, and the
third through the isolation or field region.
The structure was simulated using six input files. The first file simulates the processing in the active region
of the device, up to the point where the process diverges for the gate and the source/drain regions. The second
and third files start with the result of this first file and complete the processing for the gate region and the
source/drain region respectively. The fourth file performs an electrical parameter calculation on the resulting gate
region. The fifth file is similar to the first one, except that the processing effecting the field region of the device is
simulated. The sixth file completes the field region processing.
The processing sequence used is listed below.
1. The process begins with a high resistivity, , p-type substrate.
2. A 400 Angstrom pad layer of silicon dioxide is grown.
3. An 800 Angstrom layer of silicon nitride is deposited on top of the silicon dioxide.
4. The nitride is stripped from the areas outside of the active regions.
5. Boron is ion-implanted to increase the p doping at the surface in the field regions.
6. The field regions are then oxidized for three hours at 1000 degrees centigrade in a wet
oxygen ambient.
7. Etch to the silicon surface in the active regions.
8. Ion implant boron to set the threshold voltage of the device.
9. Grow the 400 Angstrom gate oxide.
10. Deposit a half micron layer of polysilicon.
11. Dope it with phosphorus using POCl3 in a predeposition furnace.
12. Etch the polysilicon from the areas outside of the gate regions.
13. Ion implant arsenic to form the source and gate regions.
14. Drive-in the source and drain diffusions for 30 minutes at 1000 degrees centigrade in a
dry oxygen ambient.
15. Open the contact holes in the gate, source, and drain regions.
16. Use CVD to deposit phosphorus doped silicon dioxide over the wafer surface.
17. Reflow the glass at 1000 degrees for 30 minutes.
18. Reopen the contact holes and deposit aluminum.