SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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10 PRELIMINARY DATA SuperH SH-5 system architecture documentation suite The SuperH SH-5 system architecture documentation suite comprises the following volumes: • SH-5 System Architecture, Volume 1: System (05-SA-10001) • SH-5 System Architecture, Volume 2: Peripherals (05-SA-10002) • SH-5 System Architecture, Volume 3: Debug (05-SA-10003) D R A FT SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA Debug/trace architecture 1.1 Overview of debug features D R A FT 1 The SH-5 debug system provides both traditional CPU debug, and advanced CPU and system debug features. A number of different features are available, the number of instances is scalable on a per-implementation basis. A brief overview of these debug features is given below. In the following description of debug features, the term ‘tool’ refers to any form of software development system, typically consisting of a computer plus a debug adaptor or emulator. 1.1.1 Communication with a tool SH-5 provides two interfaces through which it can communicate with a software development tool; a dedicated high-speed interface (called the SHdebug link) and a JTAG interface. A tool can use only one of these interfaces at a time. The SHdebug link is the preferred debug interface as communications between a tool and SH-5 is much faster using the SHdebug link rather than JTAG. However, some future SH-5 based ASICs may be pin-limited and not have enough pins available for a SHdebug link interface. The JTAG interface allows a tool to communicate with SH-5 and have access to all the on-chip debug features described in this document but at a substantially reduced performance compared with that offered by the SHdebug link. In addition to being used for system debug, the JTAG interface can also be used for its normal functions of boundary scan and internal scan. 05-SA-10003 v1.0 SH-5 System Architecture, Volume 3: Debug
Page 1 and 2: PRELIMINARY DATA SuperH TM (SH) 64-
Page 3 and 4: PRELIMINARY DATA Contents Preface 9
Page 5 and 6: PRELIMINARY DATA 5 1.8.11 DM.TRBUF
Page 7 and 8: PRELIMINARY DATA 7 3.2.5 Pin state
Page 9: PRELIMINARY DATA Preface This docum
Page 13 and 14: PRELIMINARY DATA Overview of debug
Page 15 and 16: PRELIMINARY DATA Key concepts 15 Th
Page 17 and 18: PRELIMINARY DATA Key concepts 17 Ac
Page 19 and 20: PRELIMINARY DATA Key concepts 19 1.
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Page 31 and 32: PRELIMINARY DATA CPU control 31 1.3
Page 33 and 34: PRELIMINARY DATA CPU control 33 1.3
Page 35 and 36: PRELIMINARY DATA Watchpoint channel
Page 49 and 50: PRELIMINARY DATA Debug event action
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA Reset, panic and d
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PRELIMINARY DATA Debug module 85 DM
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PRELIMINARY DATA Debug module 87
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PRELIMINARY DATA Debug module 89 Wh
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PRELIMINARY DATA Debug module 91 St
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PRELIMINARY DATA Debug module 93 Mu
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PRELIMINARY DATA Debug module 95 1.
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PRELIMINARY DATA Debug module 97 1.
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PRELIMINARY DATA Debug module 99 DM
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PRELIMINARY DATA Debug module 107 1
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PRELIMINARY DATA Debug module 117 1
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PRELIMINARY DATA Debug protocols an
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PRELIMINARY DATA WP channel type BR
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type OA
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type FP
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PRELIMINARY DATA WP channel type WP
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PRELIMINARY DATA SuperHyway bus ana
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PRELIMINARY DATA SuperHyway watchpo
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PRELIMINARY DATA Address comparison
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PRELIMINARY DATA Freezing bus maste
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PRELIMINARY DATA WP channel type PL
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PRELIMINARY DATA External debug int
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PRELIMINARY DATA SHdebug link 201 3
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PRELIMINARY DATA SHdebug link 205 T
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PRELIMINARY DATA SHdebug link 207 D
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PRELIMINARY DATA JTAG interface 213
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PRELIMINARY DATA Debug tool reset/s
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PRELIMINARY DATA Trigger functions
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PRELIMINARY DATA DBUS protocol 227
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PRELIMINARY DATA Implementation spe
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PRELIMINARY DATA Scalable parameter
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PRELIMINARY DATA Debug register add
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PRELIMINARY DATA Index A Actions 13
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PRELIMINARY DATA 267 244, . . . . .
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PRELIMINARY DATA 269 158-160, 166-1
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