SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
148 WP channel type OA
Note:
The data value/mask comparison is performed on the data passed between the WPC
and DM. This is controlled by the WPC.ADDR_IN_TRACE register (see Section
1.5.1: WPC.ADDR_IN_TRACE register definition on page 65). When programmed to
transfer data address, and 32 bits of data, DM.OA_MATCH_DATAMASK should be setup
to only match on the lower 32 bits of data written by triggering instructions. When an
OA channel hit occurs on a misaligned store instruction (STHI.Q, STLO.Q, STHI.L or
STLO.L), the 64 bits of data available for comparison are the same as the data that
would appear in a trace message. The composition of the 64 bits of data is described
in Section : Handling of misaligned store instructions on page 134.
DM.OA_MATCH_DATAVAL:
DM.OA_MATCH_DATAVAL
0x100030
Field Bits Size Volatile? Synopsis Type
DATA [63:0] 64 — Data value RW
Operation
When read
When written
HARD reset
Defines a data value which is combined with the data mask
specified in DM.OA_MATCH_DATAMASK.
Returns current value
Updates value
Undefined
Table 54: DM.OA_MATCH_DATAVAL register definition
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0