SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
26 Key concepts
WPC.IA_CHAIN_x
where x = chain ID
Field Bits Size Volatile? Synopsis Type
CHAIN_
STATE
0 1 ✓ Chain-latch state RO
Operation
When read
When written
HARD reset
1.2.9 Event counters
Contains an IA watchpoint chain-latch’s value.
The chain-latch is set whenever an IA watchpoint full-hit occurs. It is
cleared whenever an IA watchpoint full-hit does not occur. The new
value is visible to precondition checks from the next instruction
(inclusive) onwards.
Software can read the state of this latch at any time.
Returns 0 when the latch is clear and 1 when the latch is set.
Ignored
Undefined
— [63:1] 63 — Reserved RES
Operation
Reserved
When read Returns 0
When written
HARD reset 0
Ignored
Table 6: WPC.IA_CHAIN_x definition
SH-5 provides a series of event counters, these are used in conjunction with WP
channels to provide count-based matching of debug events.
D R A FT
An implementation may provide a maximum of 16 event counters, thus a 4-bit field
is used for the event counter ID. The counter has a maximum size of 64 bits.
Any particular implementation may provide fewer than 16 counters, and those
provided may have fewer than 64 bits. See Section 4.1.2: Event counters on page 242
for implementation-specific details.
A number of event counters are available, some are implemented in the WPC and
are accessible only by CPU core watchpoint channels, whilst others are
implemented in the DM and are accessible only by bus analyzer watchpoint
channels.
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SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0