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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

<strong>SH</strong>debug link 207<br />

DBUS messages<br />

A DBUS message is sent from <strong>SH</strong>-5 whenever the CPU or another bus master issues<br />

requests to the debug module’s <strong>SuperH</strong>yway target address space. For each request<br />

message sent from <strong>SH</strong>-5 there is a corresponding response message sent back from<br />

the external debug adapter or development host. The DBUS request message has<br />

the same format as the originating <strong>SuperH</strong>yway message but with the addition of a<br />

header to identify it as a DBUS message.<br />

The message type field occupies the least-significant 3-<strong>bit</strong>s of the first byte of the<br />

message. The remaining 5-<strong>bit</strong>s of this first byte are unused.<br />

DTRC messages<br />

There are two types of DTRC messages:<br />

• trigger trace messages (message type MHDR_DTRC_TRIG == 0b011)<br />

• background trace messages (message type MHDR_DTRC_BACK == 0b010).<br />

They are distinguished by the message type field, but contain exactly the same data.<br />

The debug adapter can perform different functions with these two types of trace<br />

message (using a different message type field simplifies the design of the debug<br />

adapter as the message header allows a simple comparison to be made).<br />

Typically, the debug adapter will store background trace messages in a trace buffer<br />

memory area for later analysis but will forward trigger trace messages to debug<br />

software running on the development host for immediate processing.<br />

DTRC transactions are output-only and require no response.<br />

DTRC message from <strong>SH</strong>-5<br />

Bit 0<br />

Message<br />

Type field<br />

D R A FT<br />

Trace Information<br />

BitN<br />

Figure 9: DTRC protocol<br />

No Response<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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