SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

More documents

Recommendations

Info

PRELIMINARY DATA 142 WP channel type IA Supported fields in DM.WP_IAx_PRE: ASID_ENABLE Supported fields in WPC.WP_IAx_ACTION: ACTION_EXCEPTION: Standard event handling sequence is followed. If SR.BL == ‘0’, the RESVEC/DBRVEC offset is 0x100 (to denote a synchronous debug event of type DEBUGIA). Otherwise, if SR.BL == ‘1’, the RESVEC/DBRVEC offset is 0x0 (to denote a PANIC event). EXPEVT is set to 0x900 to denote a DEBUGIA exception. In addition, the effective instruction address is placed into the SPC register. ACTION_ECOUNT supported. ACTION_CHAIN_ALTER/CHAIN_ID supported. ACTION_PCOUNT/ACTION_RESET_ALL_PCOUNT/PCOUNT_ID supported Supported fields in DM._WP_IAx_ACTION: ACTION_TRACE/TRACE_TYPE/ENABLE_TRACE_TIMESTAMP: See Table 41: IA watchpoint trace message on page 125 ACTION_TRIG_OUT: Supported ACTION_CHAIN_ALTER/CHAIN_ID Supported FREEZE_EN Not supported D R A FT SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA WP channel type OA 143 1.12 WP channel type OA Operand watchpoints trigger whenever an instruction performs a memory write within the defined range. The trigger occurs prior to the instruction executing (that is, prior to the write occurring). If SR.WATCH == 0, OA channels will not trigger. Two registers are in the WPC are used to define a start and end address, two registers in the DM are used to define a data value and data mask. 1.12.1 Match registers WPC.WP_OAx_MATCH_START where x = channel ID Field Bits Size Volatile? Synopsis Type — [4:0] 5 — Reserved RES Operation Reserved When read Returns 0 When written HARD reset 0 Ignored ADDRESS [31:5] 27 — Start address RW Operation When read When written HARD reset Defines the start address for the operand address range. See Section 1.12.2: on page 145. Returns current value D R A FT Updates value Undefined Table 52: WPC.WP_OAx_MATCH_START register definition 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
Page 1 and 2:
PRELIMINARY DATA SuperH TM (SH) 64-
Page 3 and 4:
PRELIMINARY DATA Contents Preface 9
Page 5 and 6:
PRELIMINARY DATA 5 1.8.11 DM.TRBUF
Page 7 and 8:
PRELIMINARY DATA 7 3.2.5 Pin state
Page 9 and 10:
PRELIMINARY DATA Preface This docum
Page 11 and 12:
PRELIMINARY DATA Debug/trace archit
Page 13 and 14:
PRELIMINARY DATA Overview of debug
Page 15 and 16:
PRELIMINARY DATA Key concepts 15 Th
Page 17 and 18:
PRELIMINARY DATA Key concepts 17 Ac
Page 19 and 20:
PRELIMINARY DATA Key concepts 19 1.
Page 21 and 22:
PRELIMINARY DATA Key concepts 21 1.
Page 23 and 24:
PRELIMINARY DATA Key concepts 23 La
Page 25 and 26:
PRELIMINARY DATA Key concepts 25 {W
Page 27 and 28:
PRELIMINARY DATA Key concepts 27 If
Page 29 and 30:
PRELIMINARY DATA Key concepts 29 Re
Page 31 and 32:
PRELIMINARY DATA CPU control 31 1.3
Page 33 and 34:
PRELIMINARY DATA CPU control 33 1.3
Page 35 and 36:
PRELIMINARY DATA Watchpoint channel
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
PRELIMINARY DATA Debug event action
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
Page 67 and 68:
PRELIMINARY DATA WP channel matchin
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
PRELIMINARY DATA Reset, panic and d
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
PRELIMINARY DATA Debug module 85 DM
Page 87 and 88:
PRELIMINARY DATA Debug module 87
Page 89 and 90:
PRELIMINARY DATA Debug module 89 Wh
Page 91 and 92: PRELIMINARY DATA Debug module 91 St
Page 93 and 94: PRELIMINARY DATA Debug module 93 Mu
Page 95 and 96: PRELIMINARY DATA Debug module 95 1.
Page 97 and 98: PRELIMINARY DATA Debug module 97 1.
Page 99 and 100: PRELIMINARY DATA Debug module 99 DM
Page 101 and 102: PRELIMINARY DATA Debug module 101 D
Page 107 and 108: PRELIMINARY DATA Debug module 107 1
Page 113 and 114: PRELIMINARY DATA Debug module 113
Page 117 and 118: PRELIMINARY DATA Debug module 117 1
Page 119 and 120: PRELIMINARY DATA Debug protocols an
Page 137 and 138: PRELIMINARY DATA WP channel type BR
Page 139 and 140: PRELIMINARY DATA WP channel type IA
Page 141: PRELIMINARY DATA WP channel type IA
Page 145 and 146: PRELIMINARY DATA WP channel type OA
Page 153 and 154: PRELIMINARY DATA WP channel type IV
Page 155 and 156: PRELIMINARY DATA WP channel type IV
Page 163 and 164: PRELIMINARY DATA WP channel type FP
Page 165 and 166: PRELIMINARY DATA WP channel type WP
Page 179 and 180: PRELIMINARY DATA SuperHyway bus ana
Page 181 and 182: PRELIMINARY DATA SuperHyway watchpo
Page 183 and 184: PRELIMINARY DATA Address comparison
Page 185 and 186: PRELIMINARY DATA Freezing bus maste
Page 187 and 188: PRELIMINARY DATA WP channel type PL
Page 193 and 194:
PRELIMINARY DATA WP channel type PL
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
PRELIMINARY DATA External debug int
Page 201 and 202:
PRELIMINARY DATA SHdebug link 201 3
Page 203 and 204:
Page 205 and 206:
PRELIMINARY DATA SHdebug link 205 T
Page 207 and 208:
PRELIMINARY DATA SHdebug link 207 D
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
PRELIMINARY DATA JTAG interface 213
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
PRELIMINARY DATA Debug tool reset/s
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
PRELIMINARY DATA Trigger functions
Page 227 and 228:
PRELIMINARY DATA DBUS protocol 227
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
PRELIMINARY DATA Implementation spe
Page 243 and 244:
PRELIMINARY DATA Scalable parameter
Page 245 and 246:
Page 247 and 248:
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
PRELIMINARY DATA Debug register add
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Page 265 and 266:
PRELIMINARY DATA Index A Actions 13
Page 267 and 268:
PRELIMINARY DATA 267 244, . . . . .
Page 269 and 270:
PRELIMINARY DATA 269 158-160, 166-1
show all

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?