SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug tool reset/suspend behavior 221
Debug tool connected via JTAG
A debug tool such as a Hitachi E20 connects to a SH-5 board-level product via a
JTAG debug header. For debug tools such as a Hitachi E20, the RESET signal in the
JTAG interface is an output from the target board which allows the tool to detect
when a board-level reset function has occurred, for example, when a user has
pressed the reset button.
The E20 does not have the capability to initiate a POWERON, MANUAL or DEBUG reset
via signals in the interface. However, the E20 can perform either a CPU reset or a
DEBUG reset by writing to the WPC.CPU_CTRL_ACTION register. The E20 has some
control over the type of reset performed by a board-level reset button. A RESET_MODE
signal is assigned to an E20 pin not currently connected and this allows the tool to
force a DEBUG reset when the reset button on the board is pressed.
With an appropriate design of target board, the RESET signal in the JTAG debug
interface could be bi-directional allowing the tool to initiate one type of hard reset,
either POWERON, MANUAL or DEBUG depending on board-level jumpers.
Signal Source Meaning
TCK From tool JTAG clock
TDI From tool JTAG data in
TDO From SH-5 JTAG data out
TMS From tool JTAG test mode select
TRST From tool JTAG reset. The tap controller finite state machine is reset
by TRST going low. This pin has no effect on other chip
functions.
RESET Bi-directional Tool can monitor this signal to detect when board-level
reset is initiated.
D R A FT
SUSPEND From tool CPU suspend mode following reset, sampled at the rising
edge of RESETP/RESETM. Refer to Section 3.4.3: CPU
suspend function on page 223 for more details.
Value - Description
0: CPU remains suspended following reset
1: CPU operates normally following reset
Table 77: JTAG debug header signals
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug