SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
220 Debug tool reset/suspend behavior
DEBUG reset from an SHdebug link tool can also be performed by writing to the
WPC.CPU_CTRL_ACTION register.
Signal Source Meaning
DM_CLKOUT From SH-5 SHdebug link output clock.
DM_OSYNC From SH-5 SHdebug link output sync.
DM_OUT[3:0] From SH-5 SHdebug link output data.
DM_CLKIN From tool SHdebug link input clock. Also debug module enable/disable
control, sampled at the rising edge of RESETP/RESETM.
Value - Description
0: The debug module is enabled following reset.
1: The debug module is disabled with its clock source turned
off following reset.
DM_ISYNC From tool SHdebug link input sync. Also CPU suspend mode (known
as the multi-function SUSPEND pin), sampled at the rising
edge of RESETP/RESETM.
Value - Description
0: CPU remains suspended following reset.
1: CPU operates normally following reset.
DM_IN From tool SHdebug link input data. Also provides the RESET_MODE
signal. The value is sampled during the entire period when
RESETP/RESETM are low.
Value - Description
0: Forces a DEBUG reset regardless of whether the RESETP or
RESETM pin is asserted.
1: A normal POWERON reset or MANUAL reset is initiated when
the corresponding reset pin is asserted.
D R A FT
RESET Bi-directional Reset signal driven by Tool (open drain). Tool can also
monitor this signal to detect when board-level reset is
initiated.
Table 76: SHdebug link header signals
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0