SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type PL 197
Supported actions in DM.WP_PLx_ACTION:
Note:
INTERRUPT:
Standard hardware debug handling sequence is followed.
DM.EXP_CAUSE.PL_INTERRUPT is set to denote the bus analyzer
channel. The RESVEC/DBRVEC offset is 0x200 (to denote an
asynchronous debug interrupt).
TRACE: See Table 46: PL Watchpoint trace message on page 131.
In “trace buffer” mode (see Section 1.8.3: DM FIFO/trace buffer in target system
memory on page 88) the DM writes the trace messages to target system memory using
SHwy store8 transactions. These transactions are visible to the SHwy bus analyzers,
and thus if a bus analyzer is programmed such that it will match on these
transactions, an infinite number of bus analyzer hits (and thus an infinite number of
trace messages) will be generated.
TRIG_OUT:
ECOUNT:
PCOUNT:
ALTER:
FREEZE_EN:
supported.
supported.
supported.
supported.
supported.
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug