SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
146 WP channel type OA
SHmedia
• An ST, FST, SWAP, STLO, ALLOCO or OCBI instruction.
The instruction will access memory from Aeffective upwards (for example,
mem[Aeffective +0], mem[Aeffective + 1]).
Oaddr corresponds to Aeffective with the lower 5 bits masked out.
• A STHI instruction.
The instruction will access memory from Aeffective downwards (for example,
mem[Aeffective - 0], mem[Aeffective - 1]).
Oaddr corresponds to Aeffective with the lower 5 bits masked out.
SHcompact
• All SHcompact store instructions which use the @ addressing mode.
The instruction will access memory from Aeffective upwards (for example,
mem[Aeffective +0], mem[Aeffective + 1]).
Oaddr corresponds to Aeffective with the lower 5 bits masked out.
The start and end address values (and thus the address comparator) are cache-block
size aligned. Thus they ignore the lower 5 bits of the address, and can only be set at
32-byte aligned addresses. This ensures that the OA comparator will not “miss”
accesses which would straddle narrower address settings, it also ensures that the
relevant caching instructions can correctly trigger the OA channels.
The comparison is inclusive of the match start address and the match end address:
Oaddr = (Aeffective & 0x1F)
addressMatch = ((Oaddr >= start) && (Oaddr