SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
154 WP channel type IV
WPC.WP_IVx_MATCH_MASK
where x = channel ID
Field Bits Size Volatile? Synopsis Type
— [63:32] 32 — Reserved RES
1.13.2 SHcompact mode
IV watchpoints are not supported for SHcompact instructions and will never trigger
when the SH-5 is operating in SHcompact mode.
1.13.3 Event specifics
Source CPU
Operation
Reason: Execution of an instruction whose bit pattern matches a defined bit
pattern, when used in conjunction with a mask value.
Undefined behavior
Reserved
When read Returns 0
When written
HARD reset 0
Ignored
Table 57: WPC.WP_IVx_MATCH_MASK register definition
The operation of the IVx registers is undefined if a write is made to
WPC.WP_IVX_{PRE/MATCH/ACTION}_* or to DM.WP_IVX_{PRE/ACTION} when the WP
channel is enabled.
D R A FT
Supported fields in WPC.WP_IVx_PRE:
BASIC_ENABLE, ASID_ENABLE, ASID_VALUE, SR_MD_ENABLE, ECOUNT_ENABLE,
ECOUNT_ID, CHAIN_ENABLE, CHAIN_ID.
ISAMODE_ENABLE Not supported - IV watchpoints only match for SHmedia
instructions.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0