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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

50 Debug event actions<br />

WPC.WP_nx_ACTION<br />

where<br />

n = {IA/OA/IV}<br />

x = channel ID (relative to N)<br />

Field Bits Size Volatile? Synopsis Type<br />

ACTION_ECOUNT 1 1 — Event count decrement enable RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Enables or disables decrement of an event counter for the WP<br />

channel. The event counter is specified by the ECOUNT_ID field<br />

of this register.<br />

Section 1.6: WP channel matching on page 66 defines the<br />

terms used below.<br />

Value - Description<br />

0: event count decrement disabled<br />

1: if PARTIAL_WP_HIT, decrement enabled. No other action will<br />

occur unless the specified event counter contains 0.<br />

Returns current value<br />

Updates value<br />

Undefined<br />

ECOUNT_ID [5:2] 4 — Event counter ID RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Defines the event counter used in the debug event match. See<br />

Section 4.1.2: Event counters on page 242. Only those event<br />

counters located in the WPC can be used. If the value in this<br />

field refers to a DM event counter, no counter decrement action<br />

occurs.<br />

Returns current value<br />

Updates value<br />

D R A FT<br />

Undefined<br />

Table 18: WPC.WP_{IA/OA/IV}x_ACTION register definition<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

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