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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

160 WP channel type BR<br />

DM.WP_BR_FILTER<br />

0x100028<br />

Field Bits Size Volatile? Synopsis Type<br />

— [63:23] 41 — Reserved RES<br />

1.14.2 Event specifics<br />

Source CPU<br />

Operation<br />

Reason: Execution of an instruction which performs a branch, or launch of a trap or<br />

interrupt handler.<br />

Undefined behavior<br />

The operationsof the BR register are undefined as writing to other fields in<br />

DM.WP_BRX_FILTER when the WP channel is enabled.<br />

WPC.WP_BRX_PRE does not exist.<br />

DM.WP_BRX_PRE does not exist.<br />

Reserved<br />

When read Returns 0<br />

When written<br />

HARD reset 0<br />

Ignored<br />

Table 58: DM.WP_BR_FILTER register definition<br />

WPC.WP_BRX_ACTION does not exist.<br />

DM.WP.BRX_ACTION does not exist<br />

D R A FT<br />

Some ACTION <strong>bit</strong>s are available in DM.WP_BRX_FILTER:<br />

ACTION_TRACE/TRACE_TYPE Is implicit - there is no ACTION_TRACE <strong>bit</strong> in<br />

DM.WP_BRX_FILTER. Thus background trace messages are always generated for the<br />

BR channel when it triggers.<br />

TRACE_TYPE/ENABLE_TRACE_TIMESTAMP See Table 44: BR watchpoint trace message<br />

on page 129.<br />

ACTION_TRIG_OUT: Supported.<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

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