SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
192 WP channel type PL
DM.WP_PLx_CTRL
where x= channel id
Field Bits Size Volatile? Synopsis Type
OPCODE_MSK [55:48] 8 — Transaction opcode mask RW
Operation
When read
When written
HARD reset
Defines which bits in the OPCODE_VAL field must match for the
watchpoint to trigger.
A value of ‘1’ in a bit position causes the watchpoint comparator to
ignore the corresponding bit of the OPCODE_VAL field, a value of ‘0’
in a bit position causes the watchpoint comparator include the bit
in the comparison.
Thus, a value of 0xFF causes the opcode field in each bus request
and response to be ignored and the watchpoint will match all
opcodes.
Returns current value
Updates current value
Undefined
OPCODE_VAL [63:56] 8 — Transaction opcode value RW
Operation
When read
When written
HARD reset
Combined with the OPCODE_MSK field and is matched against the
8-bit opcode field of each SuperHyway bus request and response.
Returns current value
Updates current value
Undefined
Table 67: DM.WP_PLx_CTRL register definition
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0