SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 178 WP channel type WPC_PERF D R A FT SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA SuperHyway bus analyzer 2.1 Introduction D R A FT 2 As part of SH-5’s on-chip debug capability, the SuperHyway router contains a bus analyzer, which provides two SuperHyway watchpoints (WP channel PL). These provide the same set of pre and action conditions as the other watchpoint channels (Section 1.6: WP channel matching on page 66 and Section 1.5: Debug event actions on page 48). In addition, an extra action feature is available to stop a specific bus initiator from making any further bus requests, that is, to freeze a bus master. The bus analyzer includes a bus capture buffer for capturing part of a bus request or bus response (called a token) whenever a bus watchpoint hit occurs. A token includes the transaction header plus one 64-bit data word, regardless of the size of the bus transaction. These captured tokens can be sent to the debug module and used to create trace messages which are written to the debug module FIFO, from which they can be sent to a specified destination (see Section 1.8: Debug module on page 85). The capture buffer is memory-mapped and when trace mode is not enabled, debug software can directly read a token from the capture buffer. It is also possible to use the bus analyzers, in conjunction with performance counters (Section 1.1.7: Performance counters on page 14) to capture selected performance parameters of the SuperHyway bus to allow system software to “tune” the parameters of individual application-specific modules or bus arbiters. 05-SA-10003 v1.0 SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Key concepts 25 {W
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PRELIMINARY DATA Key concepts 29 Re
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PRELIMINARY DATA CPU control 31 1.3
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PRELIMINARY DATA CPU control 33 1.3
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PRELIMINARY DATA Watchpoint channel
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA Reset, panic and d
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PRELIMINARY DATA Debug module 85 DM
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PRELIMINARY DATA Debug module 87
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PRELIMINARY DATA Debug module 89 Wh
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PRELIMINARY DATA Debug module 91 St
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PRELIMINARY DATA Debug module 93 Mu
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PRELIMINARY DATA Debug module 95 1.
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PRELIMINARY DATA Debug module 97 1.
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PRELIMINARY DATA Debug module 99 DM
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PRELIMINARY DATA Debug module 101 D
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PRELIMINARY DATA Debug module 107 1
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PRELIMINARY DATA Debug module 113
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PRELIMINARY DATA Debug module 117 1
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PRELIMINARY DATA Debug protocols an
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Page 181 and 182: PRELIMINARY DATA SuperHyway watchpo
Page 183 and 184: PRELIMINARY DATA Address comparison
Page 185 and 186: PRELIMINARY DATA Freezing bus maste
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Page 199 and 200: PRELIMINARY DATA External debug int
Page 201 and 202: PRELIMINARY DATA SHdebug link 201 3
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Page 207 and 208: PRELIMINARY DATA SHdebug link 207 D
Page 213 and 214: PRELIMINARY DATA JTAG interface 213
Page 219 and 220: PRELIMINARY DATA Debug tool reset/s
Page 225 and 226: PRELIMINARY DATA Trigger functions
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PRELIMINARY DATA DBUS protocol 229
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PRELIMINARY DATA Implementation spe
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PRELIMINARY DATA Scalable parameter
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PRELIMINARY DATA Debug register add
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PRELIMINARY DATA Index A Actions 13
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PRELIMINARY DATA 267 244, . . . . .
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PRELIMINARY DATA 269 158-160, 166-1
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