SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
14 Key concepts
1.1.7 Performance counters
A number of CPU based events can be setup to increment a number of performance
counters. These can be used to count arbitrary debug events from the CPU and the
bus analyzers.
CPU performance monitor channels are also available which allow a number of
distinct CPU states (cache hits/misses, interrupts taken) to be observed.
1.2 Key concepts
Note:
This section defines some key concepts and mechanisms associated with the debug
system.
The following “shorthand” terms are used throughout this document:
• WPC - watchpoint controller.
• DM - debug module.
• BA - bus analyzer.
• WP - watchpoint. Used as in “WP channel”.
Some WP channels are implemented in the WPC, others are implemented in the
debug module or the bus analyzers.
1.2.1 SHdebug link
The SHdebug link is one of the two debug interfaces which can be selected for
target/tool communications. It provides a full-duplex interface, with a 1-bit wide
input path, and a 4-bit wide output path. It is implemented as part of the debug
module (Section 1.9: Debug protocols and interfaces on page 118). The design of this
module allows the width of the output data path to be increased to meet the
debugging bandwidth needs of different applications.
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0