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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

168 WP channel type WPC_PERF<br />

WPC.WP_WPC_PERFx_MATCH_TYPE<br />

where x = channel ID<br />

Field Bits Size Volatile? Synopsis Type<br />

OCACHE_MISS 5 1 — Operand Cache Miss RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

See Section 1.18.2: Operand cache access types on<br />

page 176.<br />

Results in either 0 or 1 increments per instruction.<br />

Returns current value<br />

Updates value<br />

Undefined<br />

OCACHE_ALIAS 6 1 — Operand Cache Alias RW<br />

NONCACHE_<br />

ACCESS<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

See Section 1.18.2: Operand cache access types on<br />

page 176.<br />

Results in either 0 or 1 increments per instruction.<br />

Returns current value<br />

Updates value<br />

Undefined<br />

7 1 — Non-cache Access RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

See Section 1.18.2: Operand cache access types on<br />

page 176.<br />

Results in either 0 or 1 increments per instruction.<br />

Returns current value<br />

Updates value<br />

D R A FT<br />

Undefined<br />

Table 60: WPC.WP_WPC_PERFx_MATCH_TYPE register definition<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug 05-SA-10003 v1.0

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