SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
234 DBUS protocol
Load32
Request
OPC[7:0]
ADDR[31:0]
SRC[7:0]
TID[7:0]
MSK[7:0]
Response
R_OPC[7:0]
R_SRC[7:0]
R_TID[7:0]
R_DATA[255:0]
Opcode Load32 (0x51).
Address, where ADDR[31:24] identifies the module.
ADDR[23:5] specifies the offset within the module
ADDR[4:3] specifies the address of the critical word within a 32
byte quantity (see Section 3.6.5: Critical word ordering on
page 229).
ADDR[2:0] is not significant.
Source identifier, defined by the system not the module.
Transaction identifier, defined by the module not the system.
Byte significance within data (‘1’ == significant, ‘0’ == not
significant).
A single 8 bit mask value is supplied with the request, this value
is used for the four 8 byte loads which will be performed by this
transaction.
When dealing with Load32 requests issued from SH-5 to the
debug link, the off-chip protocol handling software and hardware
can be simplified by ignoring the mask, and thus supplying the
R_DATA field of the response with all bytes containing valid data
(that is, as if MSK was supplied as a 32-bit value of 0xFFFFFFFF).
When a debug tool issues a Load32 request to SH-5, it must be
aware that SH-5 will use the same MSK value for the four 8 byte
load operations.
See Table 81: DBUS mask/address mapping for big and little
endian modes on page 230.
D R A FT
Response type, either 0x80 for Success, or 0x81 for Failure.
Copy of SRC.
Copy of TID.
Response data.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0